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1. 发明授权

US08614126B1 Method of making a three-dimensional memory array with etch stop 有权
标题翻译：制造具有蚀刻停止的三维存储阵列的方法
公开(公告)号：US08614126B1
公开(公告)日：2013-12-24
申请号：US13586413
申请日：2012-08-15
申请人： Yao-Sheng Lee , Johann Alsmeier
发明人： Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L21/8238
CPC分类号： H01L27/11551 , H01L21/764 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.
摘要翻译：一种包括衬底和半导体沟道的三维存储器件。半导体通道的至少一个端部基本上垂直于衬底的主表面延伸。该器件还包括位于半导体通道附近的至少一个电荷存储区域以及具有基本上平行于衬底的主表面延伸的条带形状的多个控制栅极电极。多个控制栅电极至少包括位于第一器件级的第一控制栅电极和位于位于衬底的主表面上方且低于第一器件电平的第二器件电平的第二控制栅电极。该器件还包括位于衬底和多个控制栅电极之间的蚀刻停止层。

2. 发明授权

US08330208B2 Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof 有权
标题翻译：超高密度单片三维垂直NAND串存储器件及其制造方法
公开(公告)号：US08330208B2
公开(公告)日：2012-12-11
申请号：US13451009
申请日：2012-04-19
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L29/788
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
摘要翻译：单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

3. 发明申请

US20150076584A1 HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION 有权
标题翻译：高比例记忆孔通道接触形成
公开(公告)号：US20150076584A1
公开(公告)日：2015-03-19
申请号：US14225176
申请日：2014-03-25
申请人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
发明人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
IPC分类号： H01L29/788 , H01L29/792 , H01L21/28
CPC分类号： H01L21/28282 , H01L21/28273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion.
摘要翻译：一种存储器件和一种制造存储器件的方法，所述存储器件包括在衬底上形成突起，在所述突起上方形成蚀刻停止层，以及在所述蚀刻停止层上方的交替材料层堆叠。所述方法还包括将所述叠层蚀刻到所述蚀刻停止层以形成具有靠近所述蚀刻停止层的第一宽度尺寸的存储器开口，蚀刻所述蚀刻停止层以在所述突起与所述存储器开口的底部之间提供空隙区域，其中所述空隙区域具有大于所述第一宽度尺寸的第二宽度尺寸，在所述存储器开口的侧壁上并且在所述突起的顶表面上方的所述空隙区域内形成记忆膜，蚀刻所述存储膜以暴露所述突起并且在与所述突起电耦合的所述存储器开口中形成半导体通道。

4. 发明申请

US20140008714A1 Three Dimensional NAND Device and Method of Charge Trap Layer Separation and Floating Gate Formation in the NAND Device 有权
标题翻译： NAND器件中的三维NAND器件和电荷陷阱层分离和浮栅形成的方法
公开(公告)号：US20140008714A1
公开(公告)日：2014-01-09
申请号：US13544328
申请日：2012-07-09
申请人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
发明人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
IPC分类号： H01L27/088 , H01L21/8239
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/7682 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
摘要翻译：单片三维NAND串包括垂直半导体通道和不同器件级别的多个控制栅电极。该串还包括阻挡介电层，电荷存储区和隧道电介质。第一控制栅电极通过位于第一和第二控制栅电极的主表面之间的气隙与第二控制栅极分离，和/或电荷存储区包括嵌入电荷存储电介质中的硅化物纳米颗粒。

5. 发明申请

US20120001252A1 ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF 有权
公开(公告)号：US20120001252A1
公开(公告)日：2012-01-05
申请号：US12827947
申请日：2010-06-30
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L27/115 , H01L21/8246 , H01L21/8247 , H01L29/788 , H01L21/336
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

6. 发明申请

US20140138760A1 THREE DIMENSIONAL NAND DEVICE AND METHOD OF CHARGE TRAP LAYER SEPARATION AND FLOATING GATE FORMATION IN THE NAND DEVICE 有权
标题翻译：三维NAND器件和NAND器件中充电陷阱层分离和浮动栅格形成的方法
公开(公告)号：US20140138760A1
公开(公告)日：2014-05-22
申请号：US14166162
申请日：2014-01-28
申请人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
发明人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/7682 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
摘要翻译：单片三维NAND串包括垂直半导体通道和不同器件级别的多个控制栅电极。该串还包括阻挡介电层，电荷存储区和隧道电介质。第一控制栅电极通过位于第一和第二控制栅电极的主表面之间的气隙与第二控制栅极分离，和/或电荷存储区包括嵌入电荷存储电介质中的硅化物纳米颗粒。

7. 发明授权

US08187936B2 Ultrahigh density vertical NAND memory device and method of making thereof 有权
标题翻译：超高密度垂直NAND存储器件及其制造方法
公开(公告)号：US08187936B2
公开(公告)日：2012-05-29
申请号：US12827947
申请日：2010-06-30
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： A method of making a monolithic three dimensional NAND string. The method includes forming a stack of alternating layers of a first material and a second material over a substrate. The first material includes a conductive or semiconductor control gate material and the second material includes an insulating material. The method also includes etching the stack to form at least one opening in the stack, selectively etching the first material to form first recesses in the first material and forming a blocking dielectric in the first recesses. The method also includes forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric, forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening and forming a semiconductor channel in the at least one opening.
摘要翻译：制造单片三维NAND串的方法。该方法包括在衬底上形成第一材料和第二材料的交替层的叠层。第一材料包括导电或半导体控制栅极材料，第二材料包括绝缘材料。该方法还包括蚀刻堆叠以在堆叠中形成至少一个开口，选择性地蚀刻第一材料以在第一材料中形成第一凹槽并在第一凹槽中形成阻挡电介质。该方法还包括在隔离电介质上的第一凹槽中形成彼此分开的多个离散的电荷存储段，在暴露在至少一个开口中的离散电荷存储段的侧壁上形成隧道电介质，并形成半导体通道在至少一个开口中。

8. 发明授权

US09460931B2 High aspect ratio memory hole channel contact formation 有权
标题翻译：高纵横比记忆孔通道接触形成
公开(公告)号：US09460931B2
公开(公告)日：2016-10-04
申请号：US14225176
申请日：2014-03-25
申请人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
发明人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L29/792 , H01L29/66 , H01L29/788
CPC分类号： H01L21/28282 , H01L21/28273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion.
摘要翻译：一种存储器件和一种制造存储器件的方法，所述存储器件包括在衬底上形成突起，在所述突起上方形成蚀刻停止层，以及在所述蚀刻停止层上方的交替材料层堆叠。所述方法还包括将所述叠层蚀刻到所述蚀刻停止层以形成具有靠近所述蚀刻停止层的第一宽度尺寸的存储器开口，蚀刻所述蚀刻停止层以在所述突起与所述存储器开口的底部之间提供空隙区域，其中所述空隙区域具有大于所述第一宽度尺寸的第二宽度尺寸，在所述存储器开口的侧壁上并且在所述突起的顶表面上方的所述空隙区域内形成记忆膜，蚀刻所述存储膜以暴露所述突起并且在与所述突起电耦合的所述存储器开口中形成半导体通道。

9. 发明申请

US20120199898A1 ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF 有权
标题翻译：超高密度垂直NAND存储器件及其制造方法
公开(公告)号：US20120199898A1
公开(公告)日：2012-08-09
申请号：US13451009
申请日：2012-04-19
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L27/115
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
摘要翻译：单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

10. 发明授权

US08658499B2 Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device 有权
标题翻译： NAND器件中的三维NAND器件和电荷陷阱层分离和浮栅形成方法
公开(公告)号：US08658499B2
公开(公告)日：2014-02-25
申请号：US13544328
申请日：2012-07-09
申请人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
发明人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
IPC分类号： H01L27/115 , H01L21/8246
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/7682 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
摘要翻译：单片三维NAND串包括垂直半导体通道和不同器件级别的多个控制栅电极。该串还包括阻挡介电层，电荷存储区和隧道电介质。第一控制栅电极通过位于第一和第二控制栅电极的主表面之间的气隙与第二控制栅极分离，和/或电荷存储区包括嵌入电荷存储电介质中的硅化物纳米颗粒。

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