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    • 2. 发明申请
    • Delayed locked loop circuit
    • 延迟锁定回路电路
    • US20070085581A1
    • 2007-04-19
    • US11544283
    • 2006-10-06
    • Young Ku
    • Young Ku
    • H03L7/06
    • H03L7/0802H03L7/0805H03L7/0812
    • A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica delay unit, a phase comparator for comparing a phase difference between the output signal of the second buffer and the output signal of the replica delay unit; and a delay line controller for controlling delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator. The DLL circuit is configured such that the first and second buffers are disabled when the power-down mode entry notifying signal corresponding to a power-down mode is provided.
    • DLL的延迟锁定环路电路包括接收掉电信号和第一时钟信号的反相信号的缓冲器; 第一和第二延迟线,分别输出与第一和第二延迟线的输出信号对应的信号的输出装置; 复制延迟单元,用于比较第二缓冲器的输出信号和复制延迟单元的输出信号之间的相位差的相位比较器; 以及延迟线控制器​​,用于通过对应于相位比较器的比较结果来控制第一延迟线和第二延迟线的延迟时间。 配置DLL电路,使得当提供与掉电模式相对应的掉电模式进入通知信号时,禁用第一和第二缓冲器。