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1. 外观设计

USD955207S1 Curtain holdback tie 有权
公开(公告)号：USD955207S1
公开(公告)日：2022-06-21
申请号：US29766744
申请日：2021-01-18
申请人： Yang Jiao , Hui Yan
设计人： Yang Jiao , Hui Yan

2. 发明授权

US09593981B2 Nanoscale porous gold film SERS template 有权
标题翻译：纳米多孔金膜SERS模板
公开(公告)号：US09593981B2
公开(公告)日：2017-03-14
申请号：US13825152
申请日：2011-09-20
申请人： Sharon M. Weiss , Yang Jiao , Judson D. Ryckman , Peter N. Ciesielski , G. Kane Jennings
发明人： Sharon M. Weiss , Yang Jiao , Judson D. Ryckman , Peter N. Ciesielski , G. Kane Jennings
IPC分类号： G01J3/02 , B82Y30/00 , B82Y40/00 , G01N21/65 , B21D22/00 , G01J3/44
CPC分类号： G01J3/0267 , B21D22/00 , B82Y30/00 , B82Y40/00 , G01J3/44 , G01N21/658
摘要： Provided are patterned nanoporous gold (“P-NPG”) films that may act as at least one of an effective and stable surface-enhanced Raman scattering (“SERS”) substrate. Methods of fabricating the P-NPG films using a low-cost stamping technique are also provided. The P-NPG films may provide uniform SERS signal intensity and SERS signal intensity enhancement by a factor of at least about 1×107 relative to the SERS signal intensity from a non-enhancing surface.
摘要翻译：提供可以作为有效和稳定的表面增强拉曼散射（“SERS”）底物中的至少一种的图案化纳米多孔金（“P-NPG”）膜。还提供了使用低成本冲压技术制造P-NPG膜的方法。相对于来自非增强表面的SERS信号强度，P-NPG膜可以提供均匀的SERS信号强度和SERS信号强度增强因子至少约1×10 7。

3. 发明申请

US20060061596A1 Partial guardband clipping 有权
标题翻译：部分防护带剪辑
公开(公告)号：US20060061596A1
公开(公告)日：2006-03-23
申请号：US10943488
申请日：2004-09-17
申请人： Yang Jiao
发明人： Yang Jiao
IPC分类号： G06T11/20 , G09G5/00
CPC分类号： G06T15/30
摘要： A method for rendering a visible portion of an image that includes a plurality of graphics primitives. The size of the graphics primitives may be large and require the use of floating point numbers to represent the vertices. When the graphics primitives have a common vertex that is visible, the edge functions for the primitive are computed so as to avoid the common vertex becoming different for the different primitives. If the other vertices of the graphics primitives lie outside a bounding rectangle, then a vertex is formed at the intersection of the bounding rectangle and the graphics primitive. Fixed point numbers for the common vertex and other vertices including intersection vertices are then used to compute edge functions of the primitive and the primitive is rendered using the edge functions. If the common vertex is not visible, then floating point numbers are used to compute the edge functions.
摘要翻译：一种用于渲染包括多个图形基元的图像的可视部分的方法。图形基元的大小可能很大，并且需要使用浮点数来表示顶点。当图形基元具有可见的公共顶点时，计算基元的边缘函数，以避免不同基元的公共顶点变得不同。如果图形基元的其他顶点位于边界矩形之外，则在边界矩形和图形基元的交点处形成顶点。然后使用公共顶点和包括交点顶点的其他顶点的固定点编号来计算图元的边缘函数，并使用边缘函数渲染图元。如果公共顶点不可见，则使用浮点数来计算边缘函数。

4. 外观设计

USD1052383S1 Curtain holder 有权
公开(公告)号：USD1052383S1
公开(公告)日：2024-11-26
申请号：US29890649
申请日：2023-04-26
申请人： Yang Jiao
设计人： Yang Jiao
摘要： FIG. 1 is a front, right and top perspective view of a curtain holder, showing my design.
FIG. 2 is a front elevation view thereof.
FIG. 3 is a rear elevation view thereof.
FIG. 4 is a left side elevation view thereof.
FIG. 5 is a right side elevation view thereof.
FIG. 6 is a top plan view thereof.
FIG. 7 is a bottom plan view thereof.
FIG. 8 is another perspective view of the curtain holder in another state; and,
FIG. 9 is a front perspective view of the curtain holder showing a state in use.
The broken lines depict an environment of use and form no part of the claim.

5. 发明申请

US20130182249A1 NANOSCALE POROUS GOLD FILM SERS TEMPLATE 有权
标题翻译：纳米多孔金箔膜模板
公开(公告)号：US20130182249A1
公开(公告)日：2013-07-18
申请号：US13825152
申请日：2011-09-20
申请人： Sharon M. Weiss , Yang Jiao , Judson D. Ryckman , Peter N. Ciesielski , G. Kane Jennings
发明人： Sharon M. Weiss , Yang Jiao , Judson D. Ryckman , Peter N. Ciesielski , G. Kane Jennings
IPC分类号： G01J3/02 , B21D22/00 , G01J3/44
CPC分类号： G01J3/0267 , B21D22/00 , B82Y30/00 , B82Y40/00 , G01J3/44 , G01N21/658
摘要： Provided are patterned nanoporous gold (“P-NPG”) films that may act as at least one of an effective and stable surface-enhanced Raman scattering (“SERS”) substrate. Methods of fabricating the P-NPG films using a low-cost stamping technique are also provided. The P-NPG films may provide uniform SERS signal intensity and SERS signal intensity enhancement by a factor of at least about 1×107 relative to the SERS signal intensity from a non-enhancing surface.
摘要翻译：提供可以作为有效和稳定的表面增强拉曼散射（“SERS”）底物中的至少一种的图案化纳米多孔金（“P-NPG”）膜。还提供了使用低成本冲压技术制造P-NPG膜的方法。相对于来自非增强表面的SERS信号强度，P-NPG膜可以提供均匀的SERS信号强度和SERS信号强度增强因子至少约1×10 7。

6. 发明申请

US20050068321A1 Anti-aliasing line pixel coverage calculation using programmable shader 有权
标题翻译：使用可编程着色器的抗锯齿线像素覆盖计算
公开(公告)号：US20050068321A1
公开(公告)日：2005-03-31
申请号：US10671849
申请日：2003-09-25
申请人： Yang Jiao , Zhou Hong
发明人： Yang Jiao , Zhou Hong
IPC分类号： G06T5/00 , G06T11/00 , G06T11/20
CPC分类号： G06T11/203
摘要： A system and method for rendering a non-zero thickness line on a pixel-limited output device such that aliasing of the line is reduced. The edges defining a line segment are expanded to insure that any pixel touched by the line segment has its center included in the bounds of the line segment. The area of any pixel partially or fully covered by the expanded line is determined. If one edge of the line traverses the pixel, the area is determined according to whether a triangular or triangular plus parallelogram area is covered. If more than one edge of the line segment traverses a pixel, the area covered is computed based on the single edge case. With the area covered by the line segment known, the color or shading of the pixel is determined by linear interpolation between the line and the background.
摘要翻译：一种用于在像素限制输出设备上呈现非零厚度线的系统和方法，使得线的混叠减少。定义线段的边缘被扩展以确保由线段触摸的任何像素的中心包括在线段的边界中。确定由扩展线部分或完全覆盖的任何像素的面积。如果线的一个边缘穿过像素，则根据三角形或三角形加上平行四边形区域是否被覆盖来确定该区域。如果线段的多于一个边缘穿过像素，则覆盖的区域将基于单个边缘情况计算。在线段所覆盖的区域已知时，通过线与背景之间的线性插值来确定像素的颜色或阴影。

7. 发明申请

US20090001338A1 Seek-and-scan probe memory devices with nanostructures for improved bit size and resistance contrast when reading and writing to phase-change media 审中-公开
标题翻译：具有纳米结构的寻道扫描探针存储器件，用于在读取和写入相变介质时改善位大小和电阻对比度
公开(公告)号：US20090001338A1
公开(公告)日：2009-01-01
申请号：US11824382
申请日：2007-06-29
申请人： Nathan Franklin , Qing Ma , Valluri R. Rao , Mike Brown , Yang Jiao
发明人： Nathan Franklin , Qing Ma , Valluri R. Rao , Mike Brown , Yang Jiao
IPC分类号： H01L47/00
CPC分类号： G11B9/04 , B82Y10/00 , G11B9/149
摘要： A seek-and-scan probe memory device comprising a patterned capping layer over a phase-change media, where the patterned capping layer defines the bit locations on the phase-change media. The patterned capping layer may be formed from self-assembled structures. In other embodiments, nanostructures are formed on the bottom electrode below the phase-change media to focus an applied electric field from the probe, so as to increase bit density and contrast. The nanostructures may be a regular or random array of nanostructures, formed by using a self-assembling material. The nanostructures may be conductive or non-conductive. Other embodiments are described and claimed.
摘要翻译：寻找和扫描探针存储器件，其包括在相变介质上的图案化覆盖层，其中图案化覆盖层限定相变介质上的位置。图案化封盖层可以由自组装结构形成。在其他实施例中，在相变介质下方的底部电极上形成纳米结构，以将来自探针的施加的电场聚焦，以增加位密度和对比度。纳米结构可以是通过使用自组装材料形成的纳米结构的规则或随机阵列。纳米结构可以是导电的或不导电的。描述和要求保护其他实施例。

8. 发明申请

US20070067567A1 Merging entries in processor caches 审中-公开
标题翻译：合并处理器高速缓存中的条目
公开(公告)号：US20070067567A1
公开(公告)日：2007-03-22
申请号：US11229884
申请日：2005-09-19
申请人： Yang Jiao , Yiping Chen
发明人： Yang Jiao , Yiping Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/0844
摘要： The present disclosure relates to caches that are capable of improving processor performance. In some embodiments, among others, incoming requests are compared to determine whether or not those requests match. In the event that the incoming requests match, the matching requests are merged. For other embodiments, an incoming request is compared to a previous entry to determine whether the request matches the entry. In the event that the request matches the entry, the request and the entry are merged. These entries may originate from the same cache line, or, alternatively, may originate from different cache lines.
摘要翻译：本公开涉及能够提高处理器性能的高速缓存。在一些实施例中，等待传入请求被比较以确定这些请求是否匹配。在传入请求匹配的情况下，匹配的请求将被合并。对于其他实施例，将传入请求与先前条目进行比较，以确定请求是否与条目匹配。如果请求与条目匹配，则请求和条目将合并。这些条目可以来自相同的高速缓存行，或者可以来自不同的高速缓存行。

9. 发明申请

US20070186210A1 Instruction set encoding in a dual-mode computer processing environment 审中-公开
标题翻译：双模式计算机处理环境中的指令集编码
公开(公告)号：US20070186210A1
公开(公告)日：2007-08-09
申请号：US11347922
申请日：2006-02-06
申请人： Zahid Hussain , Yang Jiao
发明人： Zahid Hussain , Yang Jiao
IPC分类号： G06F9/44
CPC分类号： G06F9/30145 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/3851 , G06F9/3885
摘要： Provided is an instruction set for a dual-mode computer processing environment that includes instructions divided into multiple instruction groups. The instructions include mode-specific fields, common fields, and group-specific fields. Also a method for encoding an instruction set in a dual-mode computer processing environment is provided. The method includes dividing the instruction set into a instruction groups and defining common fields, group-specific fields, mode-specific fields, and mode-configurable fields.
摘要翻译：提供了一种用于双模式计算机处理环境的指令集，其包括分为多个指令组的指令。指令包括模式特定字段，公共字段和组特定字段。还提供了一种用于对双模计算机处理环境中的指令集进行编码的方法。该方法包括将指令集划分成指令组并定义公共字段，组特定字段，模式特定字段和模式可配置字段。

10. 发明申请

US20070091089A1 System and method for dynamically load balancing multiple shader stages in a shared pool of processing units 有权
标题翻译：在共享处理单元池中动态负载平衡多个着色器阶段的系统和方法
公开(公告)号：US20070091089A1
公开(公告)日：2007-04-26
申请号：US11406543
申请日：2006-04-19
申请人： Yang Jiao , Yijung Su
发明人： Yang Jiao , Yijung Su
IPC分类号： G06T15/50
CPC分类号： G06T15/005 , G06T15/80
摘要： The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. In one embodiment a method for graphics processing comprises assigning at least one execution unit to each of a plurality of shader units, the plurality of shader units comprising a vertex shader, a geometry shader, and a pixel shader, wherein an execution unit assigned to a given shader unit performs processing tasks for only that shader unit, determining that one of the plurality of shader units is bottlenecked, and reassigning at least one execution unit from a non-bottlenecked shader unit to the shader unit determined to be bottlenecked.
摘要翻译：本公开涉及用于在图形处理单元的顶点着色器，几何着色器和像素着色器之间管理或执行处理资源的动态分配或重新分配的新颖方法和装置。在一个实施例中，用于图形处理的方法包括将至少一个执行单元分配给多个着色器单元中的每一个，所述多个着色器单元包括顶点着色器，几何着色器和像素着色器，其中分配给给定的着色器单元仅执行着色器单元的处理任务，确定多个着色器单元中的一个是瓶颈的，并且将至少一个执行单元从非瓶颈着色器单元重新分配到被确定为瓶颈的着色器单元。

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