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1. 发明授权

US07669105B2 Generic maximum aposteriori probability decoder for use in software-defined radio systems 失效
标题翻译：用于软件定义无线电系统的通用最大后验概率解码器
公开(公告)号：US07669105B2
公开(公告)日：2010-02-23
申请号：US11501335
申请日：2006-08-09
申请人： Eran Pisek , Yan Wang , Jasmin Oz
发明人： Eran Pisek , Yan Wang , Jasmin Oz
IPC分类号： H03M13/00
CPC分类号： H03M13/3983 , H03M13/2957 , H03M13/2969 , H03M13/3911 , H03M13/6508 , H03M13/6513 , H03M13/6561
摘要： A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).
摘要翻译：可重构的最大后验概率（MAP）计算电路，其重用算术逻辑单元（ALU）硬件来计算网格的前向状态度量（α值），向后状态度量（β值）和外在信息（λ值）与MAP算法相关联。对于二进制码（即WCDMA模式）和二进制二进制码（即WiBro模式），alpha，beta和lambda计算可由相同的ALU硬件来执行。

2. 发明授权

US07483933B2 Correlation architecture for use in software-defined radio systems 有权
标题翻译：用于软件定义无线电系统的相关架构
公开(公告)号：US07483933B2
公开(公告)日：2009-01-27
申请号：US11150511
申请日：2005-06-10
申请人： Yan Wang , Eran Pisek , Jasmin Oz
发明人： Yan Wang , Eran Pisek , Jasmin Oz
IPC分类号： G06F17/15 , G06F7/52
CPC分类号： H04B1/707 , G06F17/15 , H04B1/709 , H04B2201/7071 , H04B2201/70711
摘要： A re-configurable correlation unit for correlating a sequence of chip samples comprising: 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample; and 3) a plurality of sign select units. Each sign select units receives from one add-subtract cells a first input equal to a sum (a+b) of the real bits, a, and the imaginary bits, b, and a second input equal to a difference (a−b) of the real bits, a, and the imaginary bits, b. Each sign select unit generates a real output and an imaginary output, wherein each of the real and imaginary outputs is equal to one of: 1) the sum (a+b) multiplied by one of +1 and −1 and 2) the difference (a−b) multiplied by one of +1 and −1.
摘要翻译：一种可重新配置的相关单元，用于对芯片样本序列进行相关，包括：1）存储芯片样本的存储器; 2）多个加法单元，每个加法单元从第一芯片样本接收多个实际位a和多个虚数位b; 和3）多个符号选择单元。每个符号选择单元从一个加减法单元接收等于实际比特a和b的和（a + b）的第一输入，以及虚数比特b和等于所述实数比特的差（ab）的第二输入实际位，a和虚数位，b。每个符号选择单元产生实际输出和虚拟输出，其中实际和虚拟输出中的每一个等于以下之一：1）乘以+1和-1之和的和（a + b）和2）差值（ab）乘以+1和-1之一。

3. 发明申请

US20060211387A1 Multistandard SDR architecture using context-based operation reconfigurable instruction set processors 有权
标题翻译：多标准SDR架构使用基于上下文的操作可重构指令集处理器
公开(公告)号：US20060211387A1
公开(公告)日：2006-09-21
申请号：US11142504
申请日：2005-06-01
申请人： Eran Pisek , Jasmin Oz , Yan Wang , Ronald Webb
发明人： Eran Pisek , Jasmin Oz , Yan Wang , Ronald Webb
IPC分类号： G06F3/033
CPC分类号： G06F9/30181 , G06F15/7867 , H04B1/0003 , Y02D10/12 , Y02D10/13
摘要： A software-defined radio (SDR) system comprising: 1) a reconfigurable baseband subsystem for supporting a plurality of wireless communication standards comprising a first plurality of reconfigurable context-based operation instruction set processors; and 2) a reconfigurable application subsystem for supporting a plurality of end-user applications comprising a second plurality of reconfigurable context-based operation instruction set processors. Each of the first and second pluralities of reconfigurable context-based operation instruction set processors comprises: i) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and ii) a programmable finite state machine that controls the reconfigurable data path, wherein the programmable finite state machine is capable of executing a plurality of instructions associated with a particular function.
摘要翻译：一种软件定义无线电（SDR）系统，包括：1）可重构基带子系统，用于支持多个无线通信标准，所述无线通信标准包括第一多个可重新配置的基于上下文的操作指令集处理器; 以及2）可重配置应用子系统，用于支持包括第二多个可重新配置的基于上下文的操作指令集处理器的多个最终用户应用。第一和第二多个可重新配置的基于上下文的操作指令集处理器中的每一个包括：i）包括多个可重新配置的功能块的可重构数据路径; 以及ii）可编程有限状态机，其控制所述可重构数据路径，其中所述可编程有限状态机能够执行与特定功能相关联的多个指令。

4. 发明申请

US20060184910A1 Reconfigurable interconnect for use in software-defined radio systems 有权
标题翻译：用于软件定义无线电系统的可重构互连
公开(公告)号：US20060184910A1
公开(公告)日：2006-08-17
申请号：US11142484
申请日：2005-06-01
申请人： Eran Pisek , Jasmin Oz , Yan Wang
发明人： Eran Pisek , Jasmin Oz , Yan Wang
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5045
摘要： A method of fabricating an interconnect circuit for coupling a plurality of reconfigurable component blocks that implement a defined function. The method comprises the steps of: 1) determining P possible configurations for implementing the defined function; 2) for each of the P possible configuration, determining a list of required interconnections between the plurality of reconfigurable component blocks; 3) determining from the P lists of required interconnections a minimum number, B, of data buses required to implement the P possible configurations for the defined function; 4) for each of the P possible configurations, determining the interconnections of each of the plurality of reconfigurable component blocks to each of the B buses; and 5) implementing programmable switches capable of coupling a first reconfigurable component block to a first bus only if required to implement at least one of the P possible configurations.
摘要翻译：一种制造用于耦合实现定义的功能的多个可重构部件块的互连电路的方法。该方法包括以下步骤：1）确定用于实现定义的功能的P可能配置; 2），用于确定所述多个可重配置组件块之间所需的互连的列表; 3）根据所需互连的P列确定实现所定义功能的P可能配置所需的最小数目B的数据总线; 4）对于每个P个可能的配置，确定多个可重配置组件块中的每一个与每个B总线的互连; 以及5）实现能够将第一可重新配置组件块耦合到第一总线的可编程开关，仅在需要实现P个可能配置中的至少一个时才能实现。

5. 发明申请

US20060184779A1 Pipeline controller for context-based operation reconfigurable instruction set processor 失效
标题翻译：基于上下文操作的管道控制器可重构指令集处理器
公开(公告)号：US20060184779A1
公开(公告)日：2006-08-17
申请号：US11150427
申请日：2005-06-10
申请人： Eran Pisek , Jasmin Oz , Yan Wang
发明人： Eran Pisek , Jasmin Oz , Yan Wang
IPC分类号： G06F9/44
CPC分类号： G06F8/4452 , G06F8/4432 , G06F9/381 , G06F9/4403 , Y02D10/41
摘要： An instruction execution pipeline for use in a data processor. The instruction execution pipeline comprises: 1) an instruction fetch stage; 2) a decode stage; 3) an execution stage; and 4) a write-back stage. The instruction pipeline repetitively executes a loop of instructions by fetching and decoding a first instruction associated with the loop during a first iteration of the loop, storing first decoded instruction information associated with the first instruction during the first iteration of the loop, and using the stored first decoded instruction information during at least a second iteration of the loop without further fetching and decoding of the first instruction during the at least a second iteration of the loop.
摘要翻译：用于数据处理器的指令执行流水线。指令执行流程包括：1）指令提取阶段; 2）解码阶段; 3）执行阶段; 和4）回写阶段。所述指令流水线在所述循环的第一次迭代期间重复地执行指令循环，所述指令循环通过取出和解码与所述循环相关联的第一指令，在循环的第一次迭代期间存储与所述第一指令相关联的第一解码指令信息，并且使用所存储的在循环的至少第二次迭代期间，在循环的至少第二次迭代期间，无需进一步获取和解码第一指令的第一解码指令信息。

6. 发明授权

US07856611B2 Reconfigurable interconnect for use in software-defined radio systems 有权
标题翻译：用于软件定义无线电系统的可重构互连
公开(公告)号：US07856611B2
公开(公告)日：2010-12-21
申请号：US11142484
申请日：2005-06-01
申请人： Eran Pisek , Jasmin Oz , Yan Wang
发明人： Eran Pisek , Jasmin Oz , Yan Wang
IPC分类号： H03K17/693 , H03K19/00 , G06F17/50
CPC分类号： G06F17/5045
摘要： A method of fabricating an interconnect circuit for coupling a plurality of reconfigurable component blocks that implement a defined function. The method comprises the steps of: 1) determining P possible configurations for implementing the defined function; 2) for each of the P possible configuration, determining a list of required interconnections between the plurality of reconfigurable component blocks; 3) determining from the P lists of required interconnections a minimum number, B, of data buses required to implement the P possible configurations for the defined function; 4) for each of the P possible configurations, determining the interconnections of each of the plurality of reconfigurable component blocks to each of the B buses; and 5) implementing programmable switches capable of coupling a first reconfigurable component block to a first bus only if required to implement at least one of the P possible configurations.
摘要翻译：一种制造用于耦合实现定义的功能的多个可重构部件块的互连电路的方法。该方法包括以下步骤：1）确定用于实现定义的功能的P可能配置; 2），用于确定所述多个可重配置组件块之间所需的互连的列表; 3）根据所需互连的P列确定实现所定义功能的P可能配置所需的最小数目B的数据总线; 4）对于每个P个可能的配置，确定多个可重配置组件块中的每一个与每个B总线的互连; 以及5）实现能够将第一可重新配置组件块耦合到第一总线的可编程开关，仅在需要实现P个可能配置中的至少一个时才能实现。

7. 发明授权

US07769912B2 Multistandard SDR architecture using context-based operation reconfigurable instruction set processors 有权
标题翻译：多标准SDR架构使用基于上下文的操作可重构指令集处理器
公开(公告)号：US07769912B2
公开(公告)日：2010-08-03
申请号：US11142504
申请日：2005-06-01
申请人： Eran Pisek , Jasmin Oz , Yan Wang , Ronald J. Webb
发明人： Eran Pisek , Jasmin Oz , Yan Wang , Ronald J. Webb
IPC分类号： G06F19/00
CPC分类号： G06F9/30181 , G06F15/7867 , H04B1/0003 , Y02D10/12 , Y02D10/13
摘要： A software-defined radio (SDR) system comprising: 1) a reconfigurable baseband subsystem for supporting a plurality of wireless communication standards comprising a first plurality of reconfigurable context-based operation instruction set processors; and 2) a reconfigurable application subsystem for supporting a plurality of end-user applications comprising a second plurality of reconfigurable context-based operation instruction set processors.Each of the first and second pluralities of reconfigurable context-based operation instruction set processors comprises: i) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and ii) a programmable finite state machine that controls the reconfigurable data path, wherein the programmable finite state machine is capable of executing a plurality of instructions associated with a particular function.
摘要翻译：一种软件定义无线电（SDR）系统，包括：1）可重构基带子系统，用于支持多个无线通信标准，所述无线通信标准包括第一多个可重新配置的基于上下文的操作指令集处理器; 以及2）可重配置应用子系统，用于支持包括第二多个可重新配置的基于上下文的操作指令集处理器的多个最终用户应用。第一和第二多个可重新配置的基于上下文的操作指令集处理器中的每一个包括：i）包括多个可重新配置功能块的可重构数据路径; 以及ii）可编程有限状态机，其控制所述可重构数据路径，其中所述可编程有限状态机能够执行与特定功能相关联的多个指令。

8. 发明申请

US20060184855A1 Turbo decoder architecture for use in software-defined radio systems 有权
公开(公告)号：US20060184855A1
公开(公告)日：2006-08-17
申请号：US11225479
申请日：2005-09-13
申请人： Yan Wang , Eran Pisek , Jasmin Oz
发明人： Yan Wang , Eran Pisek , Jasmin Oz
IPC分类号： H03M13/00
CPC分类号： H03M13/6561 , H03M13/2978
摘要： A reconfigurable turbo decoder comprising N processing units. Each of the N processing units receives soft input data samples and decodes the received soft input data samples. The N processing units operate independently such that a first processing unit may be selected to decode the received soft input data samples while a second processing unit may be disabled. The number of processing units selected to decode the soft input data samples is determined by a data rate of the received soft input data samples. The reconfigurable turbo decoder also comprises N input data memories that store the received soft input data samples and N extrinsic information memories that store extrinsic information generated by the N processing units. Each of the N processing units is capable of reading from and writing to each of the N input data memories and each of the N extrinsic information memories.

9. 发明申请

US20060184599A1 Correlation architecture for use in software-defined radio systems 有权
公开(公告)号：US20060184599A1
公开(公告)日：2006-08-17
申请号：US11150511
申请日：2005-06-10
申请人： Yan Wang , Eran Pisek , Jasmin Oz
发明人： Yan Wang , Eran Pisek , Jasmin Oz
IPC分类号： G06F17/15
CPC分类号： H04B1/707 , G06F17/15 , H04B1/709 , H04B2201/7071 , H04B2201/70711
摘要： A re-configurable correlation unit for correlating a sequence of chip samples comprising: 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample; and 3) a plurality of sign select units. Each sign select units receives from one add-subtract cells a first input equal to a sum (a+b) of the real bits, a, and the imaginary bits, b, and a second input equal to a difference (a−b) of the real bits, a, and the imaginary bits, b. Each sign select unit generates a real output and an imaginary output, wherein each of the real and imaginary outputs is equal to one of: 1) the sum (a+b) multiplied by one of +1 and −1 and 2) the difference (a−b) multiplied by one of +1 and −1.

10. 发明授权

US07668992B2 Context-based operation reconfigurable instruction set processor and method of operation 有权
标题翻译：基于上下文的操作可重构指令集处理器和操作方法
公开(公告)号：US07668992B2
公开(公告)日：2010-02-23
申请号：US11123313
申请日：2005-05-06
申请人： Eran Pisek , Jasmin Oz , Yan Wang
发明人： Eran Pisek , Jasmin Oz , Yan Wang
IPC分类号： G06F9/30 , G06F7/00 , H04M3/00
CPC分类号： G06F17/5045 , G06F9/30181 , G06F9/3885 , G06F9/3891 , G06F9/3897 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A reconfigurable context-based operation instruction set processor for use in a processing system capable of executing a first instruction set. The reconfigurable context-based operation instruction set processor comprises: 1) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and 2) a programmable finite state machine capable of controlling the reconfigurable data path. The programmable finite state machine is capable of executing a first plurality of context-related instructions that are a first subset of the first instruction set.
摘要翻译：一种可重构基于上下文的操作指令集处理器，用于能够执行第一指令集的处理系统。所述可重新配置的基于上下文的操作指令集处理器包括：1）包括多个可重新配置功能块的可重构数据路径; 和2）能够控制可重构数据路径的可编程有限状态机。可编程有限状态机能够执行作为第一指令集的第一子集的第一多个上下文相关指令。

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