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    • 9. 发明申请
    • 3D Integrated circuit in planar process
    • 3D平面过程中的集成电路
    • US20120074505A1
    • 2012-03-29
    • US13311115
    • 2011-12-05
    • Zhao WangWenbo TianHang Yin
    • Zhao WangWenbo TianHang Yin
    • H01L27/06
    • H01L21/8221H01L27/0688H01L27/0705
    • Techniques related to 3D integrated circuits formed on a single wafer are disclosed. According to one embodiment, an integrated circuit comprises a first device forming a first projection area on a wafer and a second device forming a second projection area on the wafer. The first projection area overlaps with the second projection area partially or completely. The area being shared between the two devices refers to the partial or complete overlapping of the projection areas of the two devices. In one embodiment, two or more devices in different layers of the integrated circuit or two or more devices at different depths in a same layer of the integrated circuit may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced.
    • 公开了在单个晶片上形成的与3D集成电路相关的技术。 根据一个实施例,集成电路包括形成晶片上的第一投影区域的第一器件和在晶片上形成第二投影区域的第二器件。 第一投影区域部分或完全与第二投影区域重叠。 两个设备之间共享的区域是指两个设备的投影区域的部分或完全重叠。 在一个实施例中,集成电路的不同层中的两个或更多个器件或集成电路的同一层中不同深度的两个或多个器件可以以某种方式共享相同晶片上的区域。 由此,可以节省芯片的面积,显着降低集成电路的芯片成本。