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1. 发明申请

US20120098043A1 SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有金属门的半导体器件及其制造方法
公开(公告)号：US20120098043A1
公开(公告)日：2012-04-26
申请号：US12911714
申请日：2010-10-25
申请人： Ya-Hsueh Hsieh , Teng-Chun Tsai , Chia-Hsi Chen , Cheng-Huei Chang , Po-Cheng Huang , Hsin-Kuo Hsu
发明人： Ya-Hsueh Hsieh , Teng-Chun Tsai , Chia-Hsi Chen , Cheng-Huei Chang , Po-Cheng Huang , Hsin-Kuo Hsu
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/823871 , H01L29/49 , H01L29/66606 , H01L29/7833
摘要： A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a semiconductor device and a contact etch stop layer (CESL) and a dielectric layer covering the semiconductor device formed thereon, wherein the semiconductor device having at least a dummy gate, performing a dummy gate removal step to form at least an opening in the semiconductor device and to simultaneously remove a portion of the CESL such that a top surface of the CESL is lower than the semiconductor device and the dielectric layer and a plurality of recesses is obtained, and performing a recess elimination step to form a substantially even surface of the dielectric layer.
摘要翻译：一种制造具有金属栅极的半导体器件的方法包括提供具有半导体器件和接触蚀刻停止层（CESL）的衬底和覆盖其上形成的半导体器件的电介质层，其中至少具有虚拟栅极的半导体器件执行模拟栅极去除步骤，以在半导体器件中形成至少一个开口，并且同时去除CESL的一部分，使得CESL的顶表面比半导体器件和电介质层低，并且获得多个凹槽，并执行凹陷消除步骤以形成电介质层的基本均匀的表面。

2. 发明授权

US08643069B2 Semiconductor device having metal gate and manufacturing method thereof 有权
标题翻译：具有金属栅极的半导体器件及其制造方法
公开(公告)号：US08643069B2
公开(公告)日：2014-02-04
申请号：US13180556
申请日：2011-07-12
申请人： Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
发明人： Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
IPC分类号： H01L29/76 , H01L21/02
CPC分类号： H01L21/28008 , H01L21/28123 , H01L21/31053 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.
摘要翻译：具有金属栅极的半导体器件包括具有形成在其中的至少一个金属栅极的多个浅沟槽隔离物（STI）的基板，以及分别位于金属的两侧的至少一对辅助虚设结构门和衬底上。

3. 发明申请

US20130015524A1 SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有金属门的半导体器件及其制造方法
公开(公告)号：US20130015524A1
公开(公告)日：2013-01-17
申请号：US13180556
申请日：2011-07-12
申请人： Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
发明人： Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28008 , H01L21/28123 , H01L21/31053 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.
摘要翻译：具有金属栅极的半导体器件包括具有形成在其中的至少一个金属栅极的至少一个金属栅极和分别位于该金属的两侧的至少一对辅助虚拟结构的基板，其中形成有多个浅沟槽隔离物（STI）门和衬底上。

4. 发明申请

US20120264302A1 CHEMICAL MECHANICAL POLISHING PROCESS 审中-公开
标题翻译：化学机械抛光工艺
公开(公告)号：US20120264302A1
公开(公告)日：2012-10-18
申请号：US13085502
申请日：2011-04-13
申请人： Chun-Wei Hsu , Teng-Chun Tsai , Chia-Lin Hsu , Po-Cheng Huang , Chia-Hsi Chen , Yen-Ming Chen , Chih-Hsun Lin
发明人： Chun-Wei Hsu , Teng-Chun Tsai , Chia-Lin Hsu , Po-Cheng Huang , Chia-Hsi Chen , Yen-Ming Chen , Chih-Hsun Lin
IPC分类号： H01L21/306
CPC分类号： H01L21/31053 , H01L21/02065 , H01L21/76224 , H01L29/66545
摘要： A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step.
摘要翻译：化学机械抛光（CMP）工艺包括以下步骤：提供基材，用酸性浆料对基材进行第一抛光步骤，以及在第一抛光步骤之后用碱性浆料对基材进行第二抛光步骤。

5. 发明申请

US20070269908A1 METHOD FOR IN-LINE CONTROLLING HYBRID CHEMICAL MECHANICAL POLISHING PROCESS 审中-公开
标题翻译：串联控制混合化学机械抛光工艺的方法
公开(公告)号：US20070269908A1
公开(公告)日：2007-11-22
申请号：US11383761
申请日：2006-05-17
申请人： Hsin-Kun Chu , Yen-Chu Chen , Teng-Chun Tsai , Chia-Hsi Chen
发明人： Hsin-Kun Chu , Yen-Chu Chen , Teng-Chun Tsai , Chia-Hsi Chen
IPC分类号： H01L21/66
CPC分类号： H01L22/26 , H01L21/31053 , H01L21/76229
摘要： A hybrid CMP system having a first platen and a second platen is provided. Two types of polish pads are mounted on the first platen and second platen. A lot of pattern wafers is prepared. Each pattern wafer has patterned features, and a first dielectric layer is disposed over a second dielectric layer and the patterned features. At least three foregoing pattern wafers of the lot are sequentially polished on the first platen to remove different amount of the first dielectric layer. Removal amount of each said foregoing pattern wafer is in-line measured and calculated to output a linear fitting curve of removal amount vs. polish time thereof. Based on the linear fitting curve, the rest of the pattern wafers of the same lot are sequentially polished on the first platen to reach a target thickness of remaining said first dielectric layer.
摘要翻译：提供了具有第一压板和第二压板的混合CMP系统。两种类型的抛光垫安装在第一压板和第二压板上。准备了许多图案晶圆。每个图案晶片具有图案化特征，并且第一介电层设置在第二介电层和图案化特征之上。批次的至少三个前述图案晶片在第一压板上顺序研磨以除去不同量的第一介电层。每个所述上述图案晶片的去除量被在线测量和计算，以输出去除量对其抛光时间的线性拟合曲线。基于线性拟合曲线，将相同批次的其余图案晶片在第一压板上顺序抛光，以达到剩余所述第一介电层的目标厚度。

6. 发明申请

US20080305610A1 METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION STRUCTURE 审中-公开
标题翻译：制造浅层隔离结构的方法
公开(公告)号：US20080305610A1
公开(公告)日：2008-12-11
申请号：US12190572
申请日：2008-08-12
申请人： Yen-Chu Chen , Hsin-Kun Chu , Teng-Chun Tsai , Chia-Hsi Chen
发明人： Yen-Chu Chen , Hsin-Kun Chu , Teng-Chun Tsai , Chia-Hsi Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/31053
摘要： A method of forming a shallow trench isolation structure includes steps of providing a substrate having a patterned mask layer formed thereon, wherein a trench is located in the substrate and the patterned mask layer exposes the trench. Thereafter, a dielectric layer is formed over the substrate to fill the trench. Then, a main polishing process with a first polishing rate is performed to remove a portion of the dielectric layer. An assisted polishing process is performed to remove the dielectric layer and a portion of the mask layer. The assisted polishing process includes steps of providing a slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate. Further, the mask layer is removed.
摘要翻译：形成浅沟槽隔离结构的方法包括提供其上形成有图案化掩模层的衬底的步骤，其中沟槽位于衬底中，并且图案化掩模层暴露沟槽。此后，在衬底上形成电介质层以填充沟槽。然后，执行具有第一抛光速率的主抛光工艺以去除电介质层的一部分。执行辅助抛光处理以去除介电层和掩模层的一部分。辅助抛光方法包括以下步骤：在第一时间段内提供浆料，然后提供溶剂并在第二时间段内执行第二抛光速率的抛光运动。第二抛光速率比第一抛光速度慢。此外，去除掩模层。

7. 发明申请

US20080261402A1 METHOD OF REMOVING INSULATING LAYER ON SUBSTRATE 审中-公开
标题翻译：在基板上去除绝缘层的方法
公开(公告)号：US20080261402A1
公开(公告)日：2008-10-23
申请号：US11736006
申请日：2007-04-17
申请人： Chan Lu , Teng-Chun Tsai , Chih-Yueh Li , Kai-Gin Yang , Chien-Chung Huang , Chia-Hsi Chen , Tzu-Hui Wu
发明人： Chan Lu , Teng-Chun Tsai , Chih-Yueh Li , Kai-Gin Yang , Chien-Chung Huang , Chia-Hsi Chen , Tzu-Hui Wu
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L21/02065
摘要： A method of removing an insulating layer on a substrate is described, including a first CMP process and a second CMP process performed in sequence, wherein the polishing slurry used in the first CMP process and that used in the second CMP process have substantially the same pH value that exceeds 7.0. A cleaning step is conducted between the first and the second CMP processes to remove a specific substance which would otherwise cause undesired particles to form in the second CMP process.
摘要翻译：描述了去除衬底上的绝缘层的方法，包括依次执行的第一CMP工艺和第二CMP工艺，其中在第一CMP工艺中使用的抛光浆料和在第二CMP工艺中使用的抛光浆料具有基本上相同的pH 价值超过7.0。在第一和第二CMP工艺之间进行清洁步骤以除去否则会在第二CMP工艺中导致不期望的颗粒形成的特定物质。

8. 发明申请

US20080045014A1 COMPLEX CHEMICAL MECHANICAL POLISHING AND METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION STRUCTURE 审中-公开
标题翻译：复合化学机械抛光及制造浅层分离结构的方法
公开(公告)号：US20080045014A1
公开(公告)日：2008-02-21
申请号：US11465457
申请日：2006-08-18
申请人： Yen-Chu Chen , Hsin-Kun Chu , Teng-Chun Tsai , Chia-Hsi Chen
发明人： Yen-Chu Chen , Hsin-Kun Chu , Teng-Chun Tsai , Chia-Hsi Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31053
摘要： A complex chemical mechanical polishing process for planarizing a structure. The process comprises steps of performing a main polishing process with a first polishing rate, wherein a slurry is provided. An assisted polishing process is then performed to planarizing the structure. The assisted polishing process comprises steps of providing the slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate.
摘要翻译：用于平面化结构的复杂化学机械抛光工艺。该方法包括以第一抛光速率进行主抛光工艺的步骤，其中提供浆料。然后进行辅助抛光处理以平坦化结构。辅助抛光方法包括以下步骤：在第一时间段内提供浆料，然后提供溶剂并在第二时间段内执行第二抛光速率的抛光运动。第二抛光速率比第一抛光速度慢。

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