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1. 发明授权

US07424077B2 Jitter sensitive maximum-a-posteriori sequence detection 有权
标题翻译：抖动敏感最大后验序列检测
公开(公告)号：US07424077B2
公开(公告)日：2008-09-09
申请号：US11105008
申请日：2005-04-13
申请人： Xueshi Yang , Erozan Mehmet Kurtas , Rohit Negi , Xun Zhang
发明人： Xueshi Yang , Erozan Mehmet Kurtas , Rohit Negi , Xun Zhang
IPC分类号： H04L7/02
CPC分类号： H04L25/03178 , G11B20/10046 , G11B20/10212
摘要： A channel detector has an anchor points inserter, a desired signal calculator, a distance calculator and a data detector. The anchor points inserter is adapted to choose values of expected transition locations for transition shifts within a received signal and to insert anchor points corresponding to the chosen values within a bit detection interval. The desired signal calculator is coupled to the anchor points inserter and is adapted to estimate desired signals corresponding to transition location information from the anchor points inserter. The distance calculator is coupled to the desired signal calculator and is adapted to generate a distance calculator output based on distances between the received signal and each of the desired signals. The data detector is coupled to the distance calculator and is adapted to identify a bit sequence corresponding to a desired signal having a minimum distance from the received signal. The data detector is adapted to generate an output based on the distance calculator output.
摘要翻译：信道检测器具有锚点插入器，期望的信号计算器，距离计算器和数据检测器。锚点插入器适于选择接收信号内的转变位移的预期转换位置的值，并且在位检测间隔内插入与所选择的值对应的锚定点。期望的信号计算器耦合到锚点插入器，并且适于估计对应于来自锚点插入器的转换位置信息的期望信号。距离计算器耦合到期望的信号计算器，并且适于基于接收信号和每个期望信号之间的距离产生距离计算器输出。数据检测器耦合到距离计算器，并且适于识别与从接收信号具有最小距离的期望信号相对应的比特序列。数据检测器适于基于距离计算器输出生成输出。

2. 发明申请

US20060233287A1 Jitter sensitive maximum-a-posteriori sequence detection 有权
标题翻译：抖动敏感最大后验序列检测
公开(公告)号：US20060233287A1
公开(公告)日：2006-10-19
申请号：US11105008
申请日：2005-04-13
申请人： Xueshi Yang , Erozan Kurtas , Rohit Negi , Xun Zhang
发明人： Xueshi Yang , Erozan Kurtas , Rohit Negi , Xun Zhang
IPC分类号： H03D1/00
CPC分类号： H04L25/03178 , G11B20/10046 , G11B20/10212
摘要： A channel detector has an anchor points inserter, a desired signal calculator, a distance calculator and a data detector. The anchor points inserter is adapted to choose values of expected transition locations for transition shifts within a received signal and to insert anchor points corresponding to the chosen values within a bit detection interval. The desired signal calculator is coupled to the anchor points inserter and is adapted to estimate desired signals corresponding to transition location information from the anchor points inserter. The distance calculator is coupled to the desired signal calculator and is adapted to generate a distance calculator output based on distances between the received signal and each of the desired signals. The data detector is coupled to the distance calculator and is adapted to identify a bit sequence corresponding to a desired signal having a minimum distance from the received signal. The data detector is adapted to generate an output based on the distance calculator output.
摘要翻译：信道检测器具有锚点插入器，期望的信号计算器，距离计算器和数据检测器。锚点插入器适于选择接收信号内的转变位移的预期转换位置的值，并且在位检测间隔内插入与所选择的值对应的锚定点。期望的信号计算器耦合到锚点插入器，并且适于估计对应于来自锚点插入器的转换位置信息的期望信号。距离计算器耦合到期望的信号计算器，并且适于基于接收信号和每个期望信号之间的距离产生距离计算器输出。数据检测器耦合到距离计算器，并且适于识别与从接收信号具有最小距离的期望信号相对应的比特序列。数据检测器适于基于距离计算器输出生成输出。

3. 发明申请

US20080151405A1 SYSTEM AND METHOD FOR DRIVE-SIDE GUARANTEE OF QUALITY OF SERVICE AND FOR EXTENDING THE LIFETIME OF STORAGE DEVICES 有权
标题翻译：驱动器质量保证和延长存储设备寿命的系统和方法
公开(公告)号：US20080151405A1
公开(公告)日：2008-06-26
申请号：US12021645
申请日：2008-01-29
申请人： Erozan Mehmet Kurtas , Mehmet Fatih Erden , Xueshi Yang
发明人： Erozan Mehmet Kurtas , Mehmet Fatih Erden , Xueshi Yang
IPC分类号： G11B27/36
CPC分类号： G11B27/36 , G11B20/10101 , G11B20/182 , G11B2020/1863
摘要： A storage device has a storage medium, a plurality of read-write mechanisms, a quality monitoring and book-keeping unit and a scheduling unit. The plurality of read-write mechanisms is coupled to the storage medium. The quality monitoring and book-keeping unit is coupled to the plurality of read-write mechanisms and is adapted to monitor at least one performance parameter associated with each read-write mechanism during operation. The scheduling unit is coupled to the quality monitoring and book-keeping unit. The scheduling unit is adapted to rank each of the plurality of read-write mechanisms according to the at least one performance parameter and to responsively schedule use of a read-write mechanism according to its rank.
摘要翻译：存储装置具有存储介质，多个读写机构，质量监视和记录单元以及调度单元。多个读写机构耦合到存储介质。质量监视和记录单元耦合到多个读写机构，并且适于在操作期间监视与每个读写机构相关联的至少一个性能参数。调度单元耦合到质量监视和记录单元。调度单元适于根据至少一个性能参数对多个读写机构中的每一个进行排序，并根据其等级响应地调度对读写机制的使用。

4. 发明授权

US09048879B1 Error correction system using an iterative product code 有权
标题翻译：纠错系统使用迭代产品代码
公开(公告)号：US09048879B1
公开(公告)日：2015-06-02
申请号：US13586710
申请日：2012-08-15
申请人： Shaohua Yang , Zining Wu , Gregory Burd , Xueshi Yang , Hongwei Song , Nedeljko Varnica
发明人： Shaohua Yang , Zining Wu , Gregory Burd , Xueshi Yang , Hongwei Song , Nedeljko Varnica
IPC分类号： H03M13/29 , H04L1/00
CPC分类号： H03M13/2945 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/23 , H03M13/2909 , H03M13/2957 , H03M13/3746 , H04L1/0065
摘要： An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.
摘要翻译：纠错系统包括使用交织分量代码和嵌入奇偶校验分量代码的迭代代码。在一些实施例中，在传输侧，在输入节点处接收的输入信号基于交织的代码进行编码，该代码编码输入数据的交错版本以产生第一组码字。第一组码字的至少一部分优选地被划分为多个符号，这些符号基于嵌入的奇偶校验码被编码以提供编码数据。类似地，在一些实施例中，在接收侧，检测所接收的数据以产生检测到的信息和软输出。检测到的信息根据嵌入的奇偶校验码进行解码以获得解码的信息。解码的信息优选地与其他软信息一起被交织的解码器使用以产生用于偏置随后的解码迭代的可靠性度量。

5. 发明授权

US09015562B1 Systems and methods for multistage error correction 有权
标题翻译：用于多级纠错的系统和方法
公开(公告)号：US09015562B1
公开(公告)日：2015-04-21
申请号：US12543006
申请日：2009-08-18
申请人： Shumei Song , Xueshi Yang
发明人： Shumei Song , Xueshi Yang
IPC分类号： G11B20/18 , G11B19/02
CPC分类号： G11B19/025 , G11B20/1833 , G11B2020/1859
摘要： In one embodiment, the present invention includes an error correction method. The error correction method comprises receiving a digital signal and processing the digital signal to perform a first error correction. The first error correction includes a first correction for data insertions or deletions and a first correction of data errors to generate a reference signal. The reference signal corresponds to the digital signal having been corrected to a first correction accuracy. The digital signal and the reference signal may be processed to perform a second correction for data insertions or deletions to generate a synchronized signal. The second correction of the digital signal is based on the reference signal, and the correction accuracy of the second correction is more accurate than the first correction accuracy.
摘要翻译：在一个实施例中，本发明包括纠错方法。误差校正方法包括接收数字信号并处理数字信号以执行第一纠错。第一纠错包括用于数据插入或删除的第一校正以及数据错误的第一校正以产生参考信号。参考信号对应于已被校正为第一校正精度的数字信号。数字信号和参考信号可以被处理以执行用于数据插入或删除的第二校正以产生同步信号。数字信号的第二校正基于参考信号，并且第二校正的校正精度比第一校正精度更准确。

6. 发明授权

US08635508B2 Systems and methods for performing concatenated error correction 有权
标题翻译：用于执行连接纠错的系统和方法
公开(公告)号：US08635508B2
公开(公告)日：2014-01-21
申请号：US13604391
申请日：2012-09-05
申请人： Xueshi Yang , Zining Wu , Seo-How Low
发明人： Xueshi Yang , Zining Wu , Seo-How Low
IPC分类号： H03M13/00
CPC分类号： H03M13/2927 , G06F11/1072 , H03M13/152 , H03M13/2903 , H03M13/2906
摘要： A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.
摘要翻译：提供了一种用于执行串联纠错的系统和方法。在一个实施方式中，用于编码数据的装置包括外编码器，用于产生与所接收的输入数据相对应的代码字，以及奇偶校验电路来计算数据的逻辑单元的奇偶校验，数据的逻辑单元从代码字获得并具有第一个逻辑单元。该装置还包括内编码器，用于基于与第一逻辑单元相对应的第一奇偶校验位产生第一逻辑单元的纠错位，并将误差校正位插入第一逻辑单元。

7. 发明授权

US08611151B1 Flash memory read performance 有权
公开(公告)号：US08611151B1
公开(公告)日：2013-12-17
申请号：US13268183
申请日：2011-10-07
申请人： Xueshi Yang
发明人： Xueshi Yang
IPC分类号： G11C11/34 , G11C16/04 , G11C7/10
CPC分类号： G11C16/0483 , G11C7/14 , G11C11/5628 , G11C11/5642 , G11C16/0408 , G11C16/06 , G11C16/26 , G11C16/28 , G11C16/344 , G11C2211/5634 , G11C2216/16
摘要： This disclosure describes techniques for reducing the number of data transmissions required to read an amount of data from multi-level-cell (MLC) flash memory. These techniques effectively increase the speed at which MLC flash memory can be read. This disclosure also describes techniques for reducing the amount of hardware and processing resources of a flash controller to read an amount of data. These techniques effectively increase the speed at which flash memory can be read by the flash controller without modifying conventional flash memories.

8. 发明授权

US08437193B1 Flash memory data recovery 有权
标题翻译：闪存数据恢复
公开(公告)号：US08437193B1
公开(公告)日：2013-05-07
申请号：US12820266
申请日：2010-06-22
申请人： Xueshi Yang
发明人： Xueshi Yang
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5621 , G11C16/04 , G11C16/349
摘要： An apparatus and method for selectively controlling application of a data recovery bias voltage are described. One example apparatus includes replenish logic configured to selectively control application of a data recovery bias voltage to a control gate associated with a cell in a flash memory apparatus. The replenish logic may be configured to select the data recovery bias voltage to replenish charge lost from a floating gate in the flash memory apparatus. The replenish logic may also be configured to control application of the data recovery bias voltage for a period of time sufficient to charge a threshold voltage (Vt) in the cell. In one embodiment, the data recovery bias voltage is based on a program voltage employed to program a value into the cell.
摘要翻译：描述了用于选择性地控制数据恢复偏置电压的应用的装置和方法。一个示例性设备包括补充逻辑，其被配置为选择性地控制数据恢复偏置电压到与闪存设备中的单元相关联的控制门的应用。补充逻辑可以被配置为选择数据恢复偏置电压以补充从闪存设备中的浮动栅极丢失的电荷。补充逻辑还可以被配置为控制数据恢复偏置电压的施加足以对单元中的阈值电压（Vt）充电的时间段。在一个实施例中，数据恢复偏置电压基于用于将值编程到单元中的编程电压。

9. 发明授权

US08416623B2 Reference voltage optimization for flash memory 有权
标题翻译： Flash存储器参考电压优化
公开(公告)号：US08416623B2
公开(公告)日：2013-04-09
申请号：US13447789
申请日：2012-04-16
申请人： Xueshi Yang
发明人： Xueshi Yang
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/30 , H01L27/115
摘要： A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages.
摘要翻译：系统包括电压发生器和参考电压设定模块。电压发生器被配置为产生要施加到存储器单元的K电压。 K电压用于确定用于读取存储器单元的参考电压，其中K是大于1的整数。参考电压设置模块被配置为选择性地将参考电压设置为K个电压中的两个相邻电压之间的值或K个电压中的两个相邻的电压之一。

10. 发明授权

US08406048B2 Accessing memory using fractional reference voltages 有权
$Accessing memory using fractional reference voltages$
标题翻译：使用分数参考电压访问存储器
公开(公告)号：US08406048B2
公开(公告)日：2013-03-26
申请号：US12535987
申请日：2009-08-05
申请人： Xueshi Yang , Zining Wu
发明人： Xueshi Yang , Zining Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/34 , G11C11/5642 , G11C16/10 , G11C16/28 , G11C2211/5634
摘要： Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of fractional reference voltages to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results.
摘要翻译：描述了使用分数参考电压访问存储器的设备，系统，方法和其他实施例。在一个实施例中，一种装置包括比较逻辑。比较逻辑将存储器单元的阈值电压与至少一对分数参考电压进行比较以产生比较结果。该装置包括至少部分地基于比较结果来确定存储器单元的位值的读取逻辑。

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