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1. 发明申请

US20120187089A1 HIGH-VOLTAGE, SUPER-VOLTAGE AND HEAVY CURRENT BREAKER 审中-公开
标题翻译：高电压，超电流和重电流断路器
公开(公告)号：US20120187089A1
公开(公告)日：2012-07-26
申请号：US13393225
申请日：2009-10-27
申请人： Xuanshu Chen , Yuan Pan , Fei Liu , Junjia He , Zhao Yuan , Ting Yin , Yan Du , Yan He
发明人： Xuanshu Chen , Yuan Pan , Fei Liu , Junjia He , Zhao Yuan , Ting Yin , Yan Du , Yan He
IPC分类号： H01H33/14
CPC分类号： H01H33/14 , H01H9/167 , H01H9/563 , H01H33/16 , H01H33/59 , H01H33/6662 , H01H2009/543
摘要： A high-voltage, super-voltage and heavy current breaker is formed by combining intelligent optical vacuum breaker modules (21) with phase selection function in series and/or parallel connection. Each vacuum breaker module (21) is connected each other in series after being connected in parallel with a resistance capacitance device or with a resistance capacitance device and a zinc oxide arrester valve plate (22). Tight coupling reactors are connected with several serial branches of the vacuum breaker module (21) simultaneously to achieve parallel connection of several serial branches of the vacuum breaker module (21). The breaker distributes the high-voltage and heavy current into the low voltage and low current serial and parallel vacuum breaker modules (21) to share.
摘要翻译：通过将智能光学真空断路器模块（21）与串联和/或并联的相位选择功能相结合，形成高压，超电压和大电流断路器。每个真空断路器模块（21）在与电阻电容器件或电阻电容器件和氧化锌避雷器阀板（22）并联连接之后彼此串联连接。紧耦合电抗器同时与真空断路器模块（21）的几个串联连接，以实现真空断路器模块（21）的几个串联分支的并联连接。断路器将高压和大电流分配到低压和低电流串联和并联真空断路器模块（21）中以共享。

2. 发明授权

US07964512B2 Method for etching high dielectric constant materials 有权
标题翻译：蚀刻高介电常数材料的方法
公开(公告)号：US07964512B2
公开(公告)日：2011-06-21
申请号：US11208573
申请日：2005-08-22
申请人： Xikun Wang , Wei Liu , Yan Du , Mei Hua Shen
发明人： Xikun Wang , Wei Liu , Yan Du , Mei Hua Shen
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L27/115 , H01L27/11521
摘要： In one implementation, a method is provided for etching a high k dielectric material in a plasma etch reactor, the method comprising plasma etching the high k dielectric material with a first plasma gas reactant mixture having BCl3. The high k dielectric material may include Al2O3 in a stack having a silicon layer. The etching may include supplying a passivation gas, for example C2H4, and may further include supplying a diluent gas such as a noble gas, for example He. In some implementations, the etching may be performed with a reactive ion etch process.
摘要翻译：在一个实施方案中，提供了一种用于在等离子体蚀刻反应器中蚀刻高k电介质材料的方法，该方法包括用具有BCl 3的第一等离子体气体反应物混合物等离子体蚀刻高k电介质材料。高k介电材料可以包括具有硅层的堆叠中的Al 2 O 3。蚀刻可以包括提供钝化气体，例如C2H4，并且还可以包括提供稀释气体，例如惰性气体，例如He。在一些实施方案中，蚀刻可以用反应离子蚀刻工艺进行。

3. 发明申请

US20130124116A1 SYSTEMS AND METHODS FOR PREDICTING THE LIFETIME OF AN ELECTROMECHANICAL DEVICE 审中-公开
标题翻译：用于预测电气设备寿命的系统和方法
公开(公告)号：US20130124116A1
公开(公告)日：2013-05-16
申请号：US13296988
申请日：2011-11-15
申请人： Yan Du , Kostadin D. Djordjev , Denis H. Endisch , Wilhelmus A. de Groot , Daniel Felnhofer
发明人： Yan Du , Kostadin D. Djordjev , Denis H. Endisch , Wilhelmus A. de Groot , Daniel Felnhofer
IPC分类号： G06F19/00
CPC分类号： G09G3/3466 , G05B23/0283 , G09G3/006 , G09G2320/048 , G09G2320/0693
摘要： This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for estimating the lifetime or remaining lifetime of an electromechanical systems (EMS) device. In one aspect, a parameter of the device, such as a release or actuation voltage, is measured. The parameter measurement is used in conjunction with a model of the aging of the device according to the measured parameter to determine an estimated remaining lifetime of the device.
摘要翻译：本公开提供了系统，方法和装置，包括在计算机存储介质上编码的计算机程序，用于估计机电系统（EMS）设备的寿命或剩余寿命。在一个方面，测量设备的参数，例如释放或致动电压。参数测量与设备的老化模型结合使用，根据测量参数确定设备的估计剩余寿命。

4. 发明授权

US07504338B2 Method of pattern etching a silicon-containing hard mask 失效
标题翻译：图案蚀刻含硅硬掩模的方法
公开(公告)号：US07504338B2
公开(公告)日：2009-03-17
申请号：US11502163
申请日：2006-08-09
申请人： Yan Du , Meihua Shen , Shashank Deshmukh
发明人： Yan Du , Meihua Shen , Shashank Deshmukh
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01J37/32174 , H01J37/321 , H01L21/31116 , H01L21/32139
摘要： Disclosed herein is a method of pattern etching a layer of a silicon-containing dielectric material. The method employs a plasma source gas including CF4 to CHF3, where the volumetric ratio of CF4 to CHF3 is within the range of about 2:3 to about 3:1; more typically, about 1:1 to about 2:1. Etching is performed at a process chamber pressure within the range of about 4 mTorr to about 60 mTorr. The method provides a selectivity for etching a silicon-containing dielectric layer relative to photoresist of 1.5:1 or better. The method also provides an etch profile sidewall angle ranging from 88° to 92° between said etched silicon-containing dielectric layer and an underlying horizontal layer. in the semiconductor structure. The method provides a smooth sidewall when used in combination with certain photoresists which are sensitive to 193 nm radiation.
摘要翻译：本文公开了一种图案蚀刻含硅介电材料层的方法。该方法采用包含CF4至CHF3的等离子体源气体，其中CF 4与CHF 3的体积比在约2:3至约3:1的范围内; 更通常为约1：1至约2：1。在约4mTorr至约60mTorr的范围内的处理室压力下进行蚀刻。该方法提供了相对于光致抗蚀剂蚀刻含硅电介质层的选择性为1.5:1或更好。该方法还提供了在所述被蚀刻的含硅介电层和下面的水平层之间从88°至92°的蚀刻轮廓侧壁角。在半导体结构中。当与某些对193nm辐射敏感的光致抗蚀剂组合使用时，该方法提供了平滑的侧壁。

5. 发明申请

US20070010099A1 Method of pattern etching a silicon-containing hard mask 失效
标题翻译：图案蚀刻含硅硬掩模的方法
公开(公告)号：US20070010099A1
公开(公告)日：2007-01-11
申请号：US11502163
申请日：2006-08-09
申请人： Yan Du , Meihua Shen , Shashank Deshmukh
发明人： Yan Du , Meihua Shen , Shashank Deshmukh
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01J37/32174 , H01J37/321 , H01L21/31116 , H01L21/32139
摘要： Disclosed herein is a method of pattern etching a layer of a silicon-containing dielectric material. The method employs a plasma source gas including CF4 to CHF3, where the volumetric ratio of CF4 to CHF3 is within the range of about 2:3 to about 3:1; more typically, about 1:1 to about 2:1. Etching is performed at a process chamber pressure within the range of about 4 mTorr to about 60 mTorr. The method provides a selectivity for etching a silicon-containing dielectric layer relative to photoresist of 1.5:1 or better. The method also provides an etch profile sidewall angle ranging from 88° to 92° between said etched silicon-containing dielectric layer and an underlying horizontal layer in the semiconductor structure. The method provides a smooth sidewall when used in combination with certain photoresists which are sensitive to 193 nm radiation.
摘要翻译：本文公开了一种图案蚀刻含硅介电材料层的方法。该方法采用等离子体源气体，其包括CF 4和CHF 3 3的体积比，其中CF 4的体积比与CHF 3 < SUB>在约2：3至约3：1的范围内; 更通常为约1：1至约2：1。在约4mTorr至约60mTorr的范围内的处理室压力下进行蚀刻。该方法提供了相对于光致抗蚀剂蚀刻含硅电介质层的选择性为1.5:1或更好。该方法还提供了在所述蚀刻的含硅介电层和半导体结构中的下面的水平层之间从88°至92°的范围内的蚀刻轮廓侧壁角。当与某些对193nm辐射敏感的光致抗蚀剂组合使用时，该方法提供了平滑的侧壁。

6. 外观设计

USD1032187S1 Makeup case with LED mirror 有权
公开(公告)号：USD1032187S1
公开(公告)日：2024-06-25
申请号：US29849537
申请日：2022-08-11
申请人： Yan Du
设计人： Yan Du
摘要： FIG. 1 is a perspective view of the makeup case with LED mirror showing my new design;
FIG. 2 is a perspective view thereof from another angle;
FIG. 3 is a front elevational view thereof;
FIG. 4 is a rear elevational view thereof;
FIG. 5 is a left side elevational view thereof;
FIG. 6 is a right side elevational view thereof;
FIG. 7 is a top plan view thereof;
FIG. 8 is a bottom plan view thereof;
FIG. 9 is an enlarged view of a portion indicated with numeric 9 in FIG. 1; and,
FIG. 10 is a perspective view thereof when the lid of the makeup case with LED mirror is open.
The broken lines shown in the drawings represent portions of the makeup case with LED mirror that form no part of the claimed design.

7. 外观设计

USD1022272S1 Bicycle light 有权
公开(公告)号：USD1022272S1
公开(公告)日：2024-04-09
申请号：US29872684
申请日：2023-03-16
申请人： Yan Du
设计人： Yan Du
摘要： FIG. 1 is a bottom perspective view of a bicycle light showing my new design.
FIG. 2 is a front view of a bicycle light.
FIG. 3 is a rear view of a bicycle light.
FIG. 4 is a left side view of a bicycle light.
FIG. 5 is a right side view of a bicycle light.
FIG. 6 is a top view of a bicycle light.
FIG. 7 is a bottom view of a bicycle light; and,
FIG. 8 is a top perspective view of a bicycle light.

8. 发明申请

US20110166045A1 WAFER SCALE PLASMONICS-ACTIVE METALLIC NANOSTRUCTURES AND METHODS OF FABRICATING SAME 审中-公开
公开(公告)号：US20110166045A1
公开(公告)日：2011-07-07
申请号：US12957921
申请日：2010-12-01
申请人： Anuj Dhawan , Michael Gerhold , Hsin-Neng Wang , Veana Mara , Tuan Vo-Dinh , Yan Du
发明人： Anuj Dhawan , Michael Gerhold , Hsin-Neng Wang , Veana Mara , Tuan Vo-Dinh , Yan Du
IPC分类号： C40B60/12 , G01N21/55 , G01N21/41 , H01L21/20 , H01L29/66 , B82Y15/00 , B82Y40/00
CPC分类号： B82Y15/00 , B82Y10/00 , B82Y20/00 , G01N21/554 , G01N21/648 , G01N21/658 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068
摘要： Plasmonics-active nanostructure substrates—developed on a wafer scale in a reliable and reproducible manner such that these plasmonics-active nanostructures have nano-scale gaps (that include but are not limited to sub-10 nm gaps or sub-5 nm gaps) that provide the highest EM field enhancement between neighboring plasmonics-active metallic or metal-coated nanostructures. The plasmonics-active nanostructure substrates relate to environmental sensing based on SERS, SPR, LSPR, and plasmon enhanced fluorescence based sensing as well as for developing plasmonics enhanced devices such as solar cells, photodetectors, and light sources. Controllable development of sub-2 nm gaps between plasmonics-active nanostructures can also be achieved. Also, the size of the nano-scale gap regions can be tuned actively (e.g., by the application of voltage or current) to develop tunable sub-5 nm gaps between plasmonic nanostructures in a controllable manner.
摘要翻译：等离子体激元 - 活性纳米结构基底以可靠和可重复的方式在晶片上开发，使得这些等离子体激元 - 活性纳米结构具有纳米级间隙（包括但不限于亚10nm间隙或次5nm间隙），在相邻的等离子体激元 - 活性金属或金属涂覆的纳米结构之间提供最高的EM场增强。等离子体激元活性纳米结构衬底涉及基于SERS，SPR，LSPR和等离子体增强荧光的感测的环境感测，以及用于开发等离子体激元增强器件，例如太阳能电池，光电检测器和光源。也可以实现等离子体激元 - 活性纳米结构之间亚-2纳米间隙的可控发展。此外，可以主动地（例如通过施加电压或电流）来调整纳米尺度间隙区域的尺寸以以可控的方式开发等离子体纳米结构之间的可调谐的5nm以下间隔。

9. 发明授权

US07928231B2 Thienopyrazoles 失效
标题翻译：噻吩吡唑
公开(公告)号：US07928231B2
公开(公告)日：2011-04-19
申请号：US12411818
申请日：2009-03-26
申请人： John Gerard Jurcak , Matthieu Barrague , Timothy Alan Gillespy , Michael Louis Edwards , Kwon Yon Musick , Philip Marvin Weintraub , Yan Du , Ramalinga M. Dharanipragada , Ashfaq Ahmad Parkar
发明人： John Gerard Jurcak , Matthieu Barrague , Timothy Alan Gillespy , Michael Louis Edwards , Kwon Yon Musick , Philip Marvin Weintraub , Yan Du , Ramalinga M. Dharanipragada , Ashfaq Ahmad Parkar
IPC分类号： C07D403/00 , C07D231/54
CPC分类号： C07D495/04
摘要： Thienopyrazoles of formula I, their preparation, pharmaceutical compositions comprising these compounds, and their pharmaceutical uses in the treatment of disease states capable of being modulated by the inhibition of the protein kinases, in particular interleukin-2 inducible tyrosine kinase (ITK).
摘要翻译：式I的噻吩并吡唑类，其制备方法，包含这些化合物的药物组合物及其在治疗能够通过抑制蛋白激酶（特别是白细胞介素-2诱导型酪氨酸激酶（ITK））调节的疾病状态的药物用途。

10. 发明申请

US20070224813A1 Device and method for etching flash memory gate stacks comprising high-k dielectric 有权
标题翻译：用于蚀刻包括高k电介质的闪存存储器栅极堆叠的器件和方法
公开(公告)号：US20070224813A1
公开(公告)日：2007-09-27
申请号：US11386054
申请日：2006-03-21
申请人： Meihua Shen , Xikun Wang , Wei Liu , Yan Du , Shashank Deshmukh
发明人： Meihua Shen , Xikun Wang , Wei Liu , Yan Du , Shashank Deshmukh
IPC分类号： C23F1/00 , H01L21/302
CPC分类号： H01L21/32136 , H01L21/31116
摘要： In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.
摘要翻译：在一个实施方式中，提供了能够蚀刻晶片以形成包括高k电介质层的器件的方法。该方法包括在具有低阴极温度的第一等离子体室中蚀刻上导电材料层，将晶片转移到第二室而不破坏真空，蚀刻第二室中的高k电介质层，以及从第二室转移晶片室到第一等离子体室，而不破坏真空。在第一室中以低阴极温度蚀刻下导电材料层。在一个实施方案中，高k电介质蚀刻是使用高温阴极的等离子体蚀刻。在另一个实施方案中，高k电介质蚀刻是反应离子蚀刻。

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