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1. 发明申请

US20130300497A1 RECONFIGURABLE INTEGRATED CIRCUIT 有权
标题翻译：可重构集成电路
公开(公告)号：US20130300497A1
公开(公告)日：2013-11-14
申请号：US13609283
申请日：2012-09-11
申请人： Xu Zhang , Chad J. Lerma , Kai Liu , Sian Lu , Hao Wang , Shayan Zhang , Wanggen Zhang
发明人： Xu Zhang , Chad J. Lerma , Kai Liu , Sian Lu , Hao Wang , Shayan Zhang , Wanggen Zhang
IPC分类号： H01L25/00
CPC分类号： H03K19/177 , H01L2224/48137 , H01L2224/49171 , H03K19/17744
摘要： A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.
摘要翻译：可重构集成电路（IC）具有包括电路输入端子和电路输出端子的IC接口端子。旁路控制器和旁路电路彼此耦合，并且耦合到至少一个电路输入端子和至少一个电路输出端子。处理电路具有耦合到旁路电路的多个电路模块。处理电路耦合到至少一个电路输入端和至少一个电路输出端。在操作中，旁路控制器控制旁路电路以选择性地将至少一对IC接口端子耦合在一起，该对包括电路输入端子之一和电路输出端子之一。当一对IC接口端子耦合在一起时，至少一个电路模块被选择性地从一对IC端子去耦合。

2. 发明授权

US08736302B2 Reconfigurable integrated circuit 有权
标题翻译：可重构集成电路
公开(公告)号：US08736302B2
公开(公告)日：2014-05-27
申请号：US13609283
申请日：2012-09-11
申请人： Xu Zhang , Chad J. Lerma , Kai Liu , Sian Lu , Hao Wang , Shayan Zhang , Wanggen Zhang
发明人： Xu Zhang , Chad J. Lerma , Kai Liu , Sian Lu , Hao Wang , Shayan Zhang , Wanggen Zhang
IPC分类号： H03K19/173 , H03K19/00 , H01L25/00
CPC分类号： H03K19/177 , H01L2224/48137 , H01L2224/49171 , H03K19/17744
摘要： A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.
摘要翻译：可重构集成电路（IC）具有包括电路输入端子和电路输出端子的IC接口端子。旁路控制器和旁路电路彼此耦合，并且耦合到至少一个电路输入端子和至少一个电路输出端子。处理电路具有耦合到旁路电路的多个电路模块。处理电路耦合到至少一个电路输入端和至少一个电路输出端。在操作中，旁路控制器控制旁路电路以选择性地将至少一对IC接口端子耦合在一起，该对包括电路输入端子之一和电路输出端子之一。当一对IC接口端子耦合在一起时，至少一个电路模块被选择性地从一对IC端子去耦合。

3. 发明申请

US20140040688A1 LOW POWER SCAN FLIP-FLOP CELL 有权
标题翻译：低功率扫描FLIP-FLOP细胞
公开(公告)号：US20140040688A1
公开(公告)日：2014-02-06
申请号：US13682749
申请日：2012-11-21
申请人： Wanggen Zhang , Sian Lu , Shayan Zhang
发明人： Wanggen Zhang , Sian Lu , Shayan Zhang
IPC分类号： G01R31/3177
CPC分类号： G01R31/318541
摘要： A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.
摘要翻译：低功率扫描触发器单元包括多路复用器，主锁存器，扫描从锁存器和数据从锁存器。主锁存器连接到多路复用器，用于产生第一个锁存信号。扫描从锁存器连接到主锁存器，并产生扫描输出（SO）信号。数据从锁存器连接到主锁存器，并根据扫描使能（SE）输入信号和第一锁存信号产生Q输出。在扫描模式期间，Q输出保持在预定电平，这消除了连接到扫描触发器单元的组合逻辑的不必要的切换，从而降低功耗。

4. 发明授权

US08880965B2 Low power scan flip-flop cell 有权
标题翻译：低功耗扫描触发器单元
公开(公告)号：US08880965B2
公开(公告)日：2014-11-04
申请号：US13682749
申请日：2012-11-21
申请人： Wanggen Zhang , Sian Lu , Shayan Zhang
发明人： Wanggen Zhang , Sian Lu , Shayan Zhang
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.
摘要翻译：低功率扫描触发器单元包括多路复用器，主锁存器，扫描从锁存器和数据从锁存器。主锁存器连接到多路复用器，用于产生第一个锁存信号。扫描从锁存器连接到主锁存器，并产生扫描输出（SO）信号。数据从锁存器连接到主锁存器，并根据扫描使能（SE）输入信号和第一锁存信号产生Q输出。在扫描模式期间，Q输出保持在预定电平，这消除了连接到扫描触发器单元的组合逻辑的不必要的切换，从而降低功耗。

5. 发明授权

US09726724B2 On-chip current test circuit 有权
公开(公告)号：US09726724B2
公开(公告)日：2017-08-08
申请号：US14554056
申请日：2014-11-26
申请人： Xiuqiang Xu , Yin Guo , Shayan Zhang , Wanggen Zhang , Xu Zhang , Yizhong Zhang
发明人： Xiuqiang Xu , Yin Guo , Shayan Zhang , Wanggen Zhang , Xu Zhang , Yizhong Zhang
IPC分类号： G01R31/26 , G01R31/3187 , G01R31/28
CPC分类号： G01R31/3187 , G01R31/2886
摘要： An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.

6. 发明申请

US20150323590A1 ON-CHIP CURRENT TEST CIRCUIT 有权
标题翻译：片内电流测试电路
公开(公告)号：US20150323590A1
公开(公告)日：2015-11-12
申请号：US14554056
申请日：2014-11-26
申请人： Xiuqiang Xu , Yin Guo , Shayan Zhang , Wanggen Zhang , Xu Zhang , Yizhong Zhang
发明人： Xiuqiang Xu , Yin Guo , Shayan Zhang , Wanggen Zhang , Xu Zhang , Yizhong Zhang
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/2886
摘要： An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.
摘要翻译：包括处理器的集成电路还具有间接测量处理器中的静态电流的片上电流测试电路。集成电路的电源电压引脚从外部测试单元接收电源电压，以向处理器供电。当处理器与电源电压隔离并且时钟信号停止时，片上测试电路在预定的测试周期T期间测量跨处理器的电压变化。电压变化提供对应于处理器的静态电流的指示。

7. 发明授权

US09110133B2 Reconfigurable circuit and decoder therefor 有权
标题翻译：可重构电路及解码器
公开(公告)号：US09110133B2
公开(公告)日：2015-08-18
申请号：US14277053
申请日：2014-05-14
申请人： Ling Wang , Huangsheng Ding , Shayan Zhang , Wanggen Zhang
发明人： Ling Wang , Huangsheng Ding , Shayan Zhang , Wanggen Zhang
IPC分类号： G01R31/3177 , G01R31/317 , H04L25/49
CPC分类号： G01R31/31701 , G01R31/3177 , H04L25/4902
摘要： A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.
摘要翻译：在可重构电路中用于解码数字脉冲的数字解码器包括具有耦合到参考脉冲输入和数据脉冲输入的输入的相位指示器模块。相位指示器模块具有提供指示在参考脉冲输入和数据脉冲输入上出现的脉冲的上升沿和下降沿的逻辑值的定时信息输出。相位解码器模块具有耦合到定时信息输出的输入，并且输出解码的二进制数据值。在操作中，相位解码器模块将定时信息输出处的至少两个逻辑值与施加到相位输入之一的脉冲的代表性的前沿和后沿的信号进行比较，以确定相位输入上的脉冲到达顺序序列，从而提供解码的二进制数据值。

8. 发明授权

US08935584B2 System and method for performing scan test 有权
标题翻译：执行扫描测试的系统和方法
公开(公告)号：US08935584B2
公开(公告)日：2015-01-13
申请号：US13681406
申请日：2012-11-19
申请人： Guoping Wan , Shayan Zhang , Wanggen Zhang
发明人： Guoping Wan , Shayan Zhang , Wanggen Zhang
IPC分类号： G01R31/3177 , G01R31/3185 , G11C29/32 , G01R31/3187
CPC分类号： G01R31/318536 , G01R31/318558 , G01R31/3187 , G11C29/32 , G11C29/40
摘要： A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.
摘要翻译：用于对诸如片上系统（SoC）的集成电路（SoC）执行扫描测试的系统可以封装在不同的封装类型中并具有不同特征的能力包括旁路信号发生器和第一扫描旁路电路。旁路信号发生器基于芯片封装信息产生第一旁路信号。第一旁路信号指示是否绕过与SoC的第一非公共电路块相关联的第一扫描链。响应于第一旁路信号绕过第一扫描链。通过启用基于包信息的部分扫描测试，可以避免由确定SoC的全扫描测试引起的无意的产量损失。

9. 发明申请

US20150048863A1 RECONFIGURABLE CIRCUIT AND DECODER THEREFOR 有权
标题翻译：可重构电路及其解码器
公开(公告)号：US20150048863A1
公开(公告)日：2015-02-19
申请号：US14277053
申请日：2014-05-14
申请人： Ling Wang , Huangsheng Ding , Shayan Zhang , Wanggen Zhang
发明人： Ling Wang , Huangsheng Ding , Shayan Zhang , Wanggen Zhang
IPC分类号： G01R31/3177
CPC分类号： G01R31/31701 , G01R31/3177 , H04L25/4902
摘要： A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.
摘要翻译：在可重构电路中用于解码数字脉冲的数字解码器包括具有耦合到参考脉冲输入和数据脉冲输入的输入的相位指示器模块。相位指示器模块具有提供指示在参考脉冲输入和数据脉冲输入上出现的脉冲的上升沿和下降沿的逻辑值的定时信息输出。相位解码器模块具有耦合到定时信息输出的输入，并且输出解码的二进制数据值。在操作中，相位解码器模块将定时信息输出处的至少两个逻辑值与施加到相位输入之一的脉冲的代表性的前沿和后沿的信号进行比较，以确定相位输入上的脉冲到达顺序序列，从而提供解码的二进制数据值。

10. 发明授权

US09343183B2 Memory device retention mode based on error information 有权
标题翻译：基于错误信息的内存设备保留模式
公开(公告)号：US09343183B2
公开(公告)日：2016-05-17
申请号：US14463674
申请日：2014-08-20
申请人： Ziyu Guo , Xiangming Kong , Shayan Zhang
发明人： Ziyu Guo , Xiangming Kong , Shayan Zhang
IPC分类号： G11C29/50 , G11C29/52 , G06F1/32 , G11C5/14 , G11C11/417 , G11C29/04
CPC分类号： G11C29/50016 , G06F1/3275 , G06F1/3296 , G11C5/147 , G11C11/417 , G11C29/50004 , G11C29/52 , G11C2029/0409 , Y02D10/14 , Y02D10/172
摘要： A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter.
摘要翻译：用于存储器件的控制器具有功率控制部分，用于在操作模式和保持模式下控制存储元件的功率。监视部分接收和监视错误信息，并且存储部分存储保留参数。在操作模式中，功率控制部分使得存储元件施加操作电压，并且在保持模式下，功率控制部分使时变电压施加到存储器。功率控制部分还使得存储元件两端的电压基于保持参数在第一保持电压和第二保持电压之间的保持模式中改变。

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