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1. 发明授权

US09635374B2 Systems and methods for coding video data using switchable encoders and decoders 有权
公开(公告)号：US09635374B2
公开(公告)日：2017-04-25
申请号：US13564686
申请日：2012-08-01
申请人： Xiaosong Zhou , Hsi-Jung Wu , Chris Y. Chung , Feng Yi
发明人： Xiaosong Zhou , Hsi-Jung Wu , Chris Y. Chung , Feng Yi
IPC分类号： H04N19/42 , H04N19/12
CPC分类号： H04N19/42 , H04N19/12
摘要： A system and method for switching between multiple encoders or decoders may be implemented to quickly and seamlessly transfer coding operations between two encoders. Before switching from a first encoder to a second encoder, the second encoder is initialized and updated with a copy of the necessary information from the first encoder. Similarly when switching from a first decoder to a second decoder, the second decoder is initialized and the necessary information from the first decoder is passed to the second decoder. A controller may monitor the system to identify a condition that would trigger an encoder switch and identify the encoder that best suits the system conditions. A shared memory unit accessible by either encoder may store the initialization information. A shared decode unit accessible by either encoder may transmit decoded frames between encoders.

2. 发明申请

US20130329799A1 PREDICTIVE VIDEO CODER WITH LOW POWER REFERENCE PICTURE TRANSFORMATION 有权
标题翻译：具有低功率参考图像转换的预测视频编码器
公开(公告)号：US20130329799A1
公开(公告)日：2013-12-12
申请号：US13755928
申请日：2013-01-31
申请人： Yao-Chung Lin , Xiaosong Zhou , Hsi-Jung Wu , Douglas Scott Price , Chris Y. Chung , Dazhong Zhang
发明人： Yao-Chung Lin , Xiaosong Zhou , Hsi-Jung Wu , Douglas Scott Price , Chris Y. Chung , Dazhong Zhang
IPC分类号： H04N7/26
CPC分类号： H04N19/51 , H04N19/503
摘要： Video coders may perform perspective transformation of reference frames during coding in a manner that conserves processing resources. When a new input frame is available for coding, a camera position for the input frame may be estimated. A video coder may search for reference pictures having similar camera positions as the position of the input frame and, for each reference picture identified, the video coder may perform a prediction search to identify a reference picture that is the best prediction match for the input frame. Once the video coder identifies a reference picture to serve as a prediction source for the input frame, the video coder may derive a transform to match the reference frame data to the input frame data and may transform the reference picture accordingly. The video coder may code the input frame using the transformed reference picture as a prediction reference and may transmit coded frame data and the camera position of the input frame to a decoder. Thus, the video coder may perform derivation and execution of transforms on a limited basis which conserves system resources.
摘要翻译：视频编码器可以在编码期间以保存处理资源的方式执行参考帧的透视变换。当新的输入帧可用于编码时，可以估计用于输入帧的摄像机位置。视频编码器可以搜索具有与输入帧的位置相似的相机位置的参考图像，并且对于识别的每个参考图像，视频编码器可以执行预测搜索以识别作为输入帧的最佳预测匹配的参考图像。一旦视频编码器识别用作输入帧的预测源的参考图像，则视频编码器可以导出将参考帧数据与输入帧数据相匹配的变换，并且可以相应地变换参考图像。视频编码器可以使用变换的参考图片作为预测参考来对输入帧进行编码，并且可以将编码的帧数据和输入帧的摄像机位置发送到解码器。因此，视频编码器可以在有限的基础上进行变换的推导和执行，从而节省系统资源。

3. 发明授权

US09414086B2 Partial frame utilization in video codecs 有权
标题翻译：视频编解码器的部分帧利用率
公开(公告)号：US09414086B2
公开(公告)日：2016-08-09
申请号：US13487498
申请日：2012-06-04
申请人： Feng Yi , David R. Conrad , Chris Y. Chung
发明人： Feng Yi , David R. Conrad , Chris Y. Chung
IPC分类号： H04N7/32 , H04N19/55 , H04N19/176 , H04N19/46 , H04N19/61 , H04N19/103 , H04N19/117 , H04N19/124 , H04N19/156 , H04N19/164 , H04N19/17 , H04N19/167 , H04N19/29 , H04N19/85
CPC分类号： H04N19/55 , H04N19/103 , H04N19/117 , H04N19/124 , H04N19/156 , H04N19/164 , H04N19/167 , H04N19/17 , H04N19/176 , H04N19/29 , H04N19/46 , H04N19/61 , H04N19/85
摘要： Embodiments of the present invention provide techniques for efficiently coding/decoding video data during circumstances where a decoder only requires or utilizes a portion of coded frames. A coder may exchange signaling with a decoder to identify unused areas of frames and prediction modes for the unused areas. An input frame may be parsed into a used area and an unused area based on the exchanged signaling. If motion vectors of the input frame are not limited to the used areas of the reference frames, the unused area of the input frame may be coded using low complexity. If the motion vectors of the input frame are limited to the used areas of the reference frames, the pixel blocks in the unused area of the input frame may not be coded, or the unused area of the input frame may be filled with gray, white, or black pixel blocks.
摘要翻译：本发明的实施例提供了在解码器仅需要或利用编码帧的一部分的情况下有效地对视频数据进行编码/解码的技术。编码器可以与解码器交换信令以识别未使用区域的帧的未使用区域和预测模式。可以基于所交换的信令将输入帧解析为使用区域和未使用区域。如果输入帧的运动矢量不限于参考帧的使用区域，则可以使用低复杂度对输入帧的未使用区域进行编码。如果输入帧的运动矢量被限制到参考帧的使用区域，则输入帧的未使用区域中的像素块可能不被编码，或者输入帧的未使用区域可以用灰色，白色，或黑色像素块。

4. 发明申请

US20120307904A1 PARTIAL FRAME UTILIZATION IN VIDEO CODECS 有权
标题翻译：视频编码器中的部分帧使用
公开(公告)号：US20120307904A1
公开(公告)日：2012-12-06
申请号：US13487498
申请日：2012-06-04
申请人： Feng Yi , David R. Conrad , Chris Y. Chung
发明人： Feng Yi , David R. Conrad , Chris Y. Chung
IPC分类号： H04N7/32 , H04N7/12
CPC分类号： H04N19/55 , H04N19/103 , H04N19/117 , H04N19/124 , H04N19/156 , H04N19/164 , H04N19/167 , H04N19/17 , H04N19/176 , H04N19/29 , H04N19/46 , H04N19/61 , H04N19/85
摘要： Embodiments of the present invention provide techniques for efficiently coding/decoding video data during circumstances where a decoder only requires or utilizes a portion of coded frames. A coder may exchange signaling with a decoder to identify unused areas of frames and prediction modes for the unused areas. An input frame may be parsed into a used area and an unused area based on the exchanged signaling. If motion vectors of the input frame are not limited to the used areas of the reference frames, the unused area of the input frame may be coded using low complexity. If the motion vectors of the input frame are limited to the used areas of the reference frames, the pixel blocks in the unused area of the input frame may not be coded, or the unused area of the input frame may be filled with gray, white, or black pixel blocks.
摘要翻译：本发明的实施例提供了在解码器仅需要或利用编码帧的一部分的情况下有效地对视频数据进行编码/解码的技术。编码器可以与解码器交换信令以识别未使用区域的帧的未使用区域和预测模式。可以基于所交换的信令将输入帧解析为使用区域和未使用区域。如果输入帧的运动矢量不限于参考帧的使用区域，则可以使用低复杂度对输入帧的未使用区域进行编码。如果输入帧的运动矢量被限制到参考帧的使用区域，则输入帧的未使用区域中的像素块可能不被编码，或者输入帧的未使用区域可以用灰色，白色，或黑色像素块。

5. 发明授权

US07694111B2 Processor employing loadable configuration parameters to reduce or eliminate setup and pipeline delays in a pipeline system 有权
标题翻译：处理器采用可加载配置参数来减少或消除管道系统中的设置和流水线延迟
公开(公告)号：US07694111B2
公开(公告)日：2010-04-06
申请号：US12033785
申请日：2008-02-19
申请人： Chris Y. Chung , Ravi A. Managuli , Yongmin Kim
发明人： Chris Y. Chung , Ravi A. Managuli , Yongmin Kim
IPC分类号： G06F9/00
CPC分类号： G06F15/8053 , G06F9/3851
摘要： A deep-pipeline system substantially reduces the overhead of setup delays and pipeline delays by dynamically controlling access of a plurality of configuration register sets by both a host central processing unit (CPU) and the stages of the pipelines. A master configuration register set is loaded with configuration parameters by the host CPU in response to an index count provided by a setup-index counter. A plurality of other counters are employed to track timing events in the system. In one embodiment, a run-index counter provides a run-index count to the first stage of the pipeline that is propagated along the stages, enabling configuration register sets to transfer configuration parameters to the stages of the pipeline when required to enable processing of a task. In an alternative embodiment, a plurality of D flip-flops sequentially propagates a state for successive registers, so that the setup-index counter is not required.
摘要翻译：深管道系统通过动态地控制主机中央处理单元（CPU）和管线的级的多个配置寄存器集的访问，大大减少了设置延迟和流水线延迟的开销。主机配置寄存器集合由主机CPU加载配置参数，以响应由设置索引计数器提供的索引计数。采用多个其他计数器来跟踪系统中的定时事件。在一个实施例中，运行索引计数器向沿着级传播的流水线的第一级提供运行索引计数，使得配置寄存器组能够在需要时将配置参数传送到流水线的各个级，以便能够处理任务。在替代实施例中，多个D触发器顺序地传播用于连续寄存器的状态，使得不需要建立索引计数器。

6. 发明申请

US20080141001A1 PROCESSOR EMPLOYING LOADABLE CONFIGURATION PARAMETERS TO REDUCE OR ELIMINATE SETUP AND PIPELINE DELAYS IN A PIPELINE SYSTEM 有权
标题翻译：处理器采用可负载配置参数来减少或消除管道系统中的设置和管道延迟
公开(公告)号：US20080141001A1
公开(公告)日：2008-06-12
申请号：US12033785
申请日：2008-02-19
申请人： Chris Y. Chung , Ravi A. Managuli , Yongmin Kim
发明人： Chris Y. Chung , Ravi A. Managuli , Yongmin Kim
IPC分类号： G06F9/30
CPC分类号： G06F15/8053 , G06F9/3851
摘要： A deep-pipeline system substantially reduces the overhead of setup delays and pipeline delays by dynamically controlling access of a plurality of configuration register sets by both a host central processing unit (CPU) and the stages of the pipelines. A master configuration register set is loaded with configuration parameters by the host CPU in response to an index count provided by a setup-index counter. A plurality of other counters are employed to track timing events in the system. In one embodiment, a run-index counter provides a run-index count to the first stage of the pipeline that is propagated along the stages, enabling configuration register sets to transfer configuration parameters to the stages of the pipeline when required to enable processing of a task. In an alternative embodiment, a plurality of D flip-flops sequentially propagates a state for successive registers, so that the setup-index counter is not required.
摘要翻译：深管道系统通过动态地控制主机中央处理单元（CPU）和管线的级的多个配置寄存器集的访问，大大减少了设置延迟和流水线延迟的开销。主机配置寄存器集合由主机CPU加载配置参数，以响应由设置索引计数器提供的索引计数。采用多个其他计数器来跟踪系统中的定时事件。在一个实施例中，运行索引计数器向沿着级传播的流水线的第一级提供运行索引计数，使得配置寄存器组能够在需要时将配置参数传送到流水线的各个级，以便能够处理任务。在替代实施例中，多个D触发器顺序地传播用于连续寄存器的状态，使得不需要建立索引计数器。

7. 发明申请

US20140064160A1 Synchronizing Uplink and Downlink Transmissions in a Wireless Device 有权
标题翻译：在无线设备中同步上行链路和下行链路传输
公开(公告)号：US20140064160A1
公开(公告)日：2014-03-06
申请号：US13604572
申请日：2012-09-05
申请人： Luciano M. Verger , Gang Lu , Hyeonkuk Jeong , Chris Y. Chung
发明人： Luciano M. Verger , Gang Lu , Hyeonkuk Jeong , Chris Y. Chung
IPC分类号： H04W72/14 , H04W52/02
CPC分类号： H04W52/0216 , H04W72/14 , Y02D70/00 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164 , Y02D70/168 , Y02D70/24
摘要： Synchronizing uplink and downlink transmissions by a wireless user equipment (UE) device. A connection with a network may be established via a wireless link with a cell. The UE may operate in an active state during first periods of time in which uplink or downlink communications may be performed between the UE and the network. The UE may operate in a reduced-power state during second periods of time in which uplink and downlink communications are not performed. The first periods of time may alternate with the second periods of time in a repeating manner. Uplink data generated by the UE may be buffered during second periods of time and transmitted during first periods of time. Buffering uplink data in this manner may prevent the UE from immediately transitioning from the reduced-power state to the active state to transmit uplink data, which may conserve battery of the UE.
摘要翻译：由无线用户设备（UE）设备同步上行链路和下行链路传输。可以通过与小区的无线链路建立与网络的连接。 UE可以在可以在UE和网络之间执行上行链路或下行链路通信的第一时间段期间在活动状态下操作。在不执行上行链路和下行链路通信的第二时间段期间，UE可以在降低功率状态下操作。第一时间段可以以重复的方式与第二时间段交替。由UE产生的上行链路数据可以在第二时间段期间被缓冲并且在第一时间段期间被发送。以这种方式缓冲上行链路数据可以阻止UE立即从降低功率状态转换到活动状态以发送上行链路数据，这可以节省UE的电池。

8. 发明授权

US07383426B2 Processor employing loadable configuration parameters to reduce or eliminate setup and pipeline delays in a pipeline system 有权
标题翻译：处理器采用可加载配置参数来减少或消除管道系统中的设置和流水线延迟
公开(公告)号：US07383426B2
公开(公告)日：2008-06-03
申请号：US10459016
申请日：2003-06-11
申请人： Chris Y. Chung , Ravi A. Managuli , Yongmin Kim
发明人： Chris Y. Chung , Ravi A. Managuli , Yongmin Kim
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F15/8053 , G06F9/3851
摘要： A deep-pipeline system substantially reduces the overhead of setup delays and pipeline delays by dynamically controlling access of a plurality of configuration register sets by both a host central processing unit (CPU) and the stages of the pipelines. A master configuration register set is loaded with configuration parameters by the host CPU in response to an index count provided by a setup-index counter. A plurality of other counters are employed to track timing events in the system. In one embodiment, a run-index counter provides a run-index count to the first stage of the pipeline that is propagated along the stages, enabling configuration register sets to transfer configuration parameters to the stages of the pipeline when required to enable processing of a task. In an alternative embodiment, a plurality of D flip-flops sequentially propagates a state for successive registers, so that the setup-index counter is not required.
摘要翻译：深管道系统通过动态地控制主机中央处理单元（CPU）和管线的级的多个配置寄存器集的访问，大大减少了设置延迟和流水线延迟的开销。主机配置寄存器集合由主机CPU加载配置参数，以响应由设置索引计数器提供的索引计数。采用多个其他计数器来跟踪系统中的定时事件。在一个实施例中，运行索引计数器向沿着级传播的流水线的第一级提供运行索引计数，使得配置寄存器组能够在需要时将配置参数传送到流水线的各个级，以便能够处理任务。在替代实施例中，多个D触发器顺序地传播用于连续寄存器的状态，使得不需要建立索引计数器。

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