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1. 发明授权

US07727892B2 Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects 有权
标题翻译：用于形成用于集成电路互连的金属 - 金属氧化物蚀刻停止/屏障的方法和装置
公开(公告)号：US07727892B2
公开(公告)日：2010-06-01
申请号：US10255930
申请日：2002-09-25
申请人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
发明人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
IPC分类号： H01L21/311
CPC分类号： H01L21/76849 , H01L21/76829 , H01L21/76834 , H01L21/76855 , H01L21/76888 , H01L21/76897 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
摘要翻译：描述了用于与金属 - 金属氧化物电迁移屏障和蚀刻停止形成互连的方法和装置。在本发明的一个实施例中，该方法包括在平坦化的互连层的顶部上沉积金属层，所述互连层具有层间电介质（ILD），其顶部与导电互连的顶部是平面的。在本发明的一个实施方案中，该方法包括使金属层与ILD反应以在ILD的顶部形成金属氧化物层。同时，金属层不会被导电互连显着地氧化，从而在导电互连上形成金属阻挡层以改善电迁移性能。金属屏障和金属氧化物层一起包括保护层。随后可以在保护层上形成第二ILD，并且保护层可以在随后的第二ILD蚀刻期间进行蚀刻停止。

2. 发明授权

US06794755B2 Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement 有权
标题翻译：用于电迁移和粘附改善的集成电路中金属互连的表面改变
公开(公告)号：US06794755B2
公开(公告)日：2004-09-21
申请号：US10400128
申请日：2003-03-25
申请人： Jose A. Maiz , Xiaorong Morrow , Thomas Marieb , Carolyn Block , Jihperng Leu , Paul McGregor , Markus Kuhn , Mitchell C. Taylor
发明人： Jose A. Maiz , Xiaorong Morrow , Thomas Marieb , Carolyn Block , Jihperng Leu , Paul McGregor , Markus Kuhn , Mitchell C. Taylor
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/32051 , H01L21/76801 , H01L21/76805 , H01L21/76807 , H01L21/76822 , H01L21/76825 , H01L21/76834 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L21/76864 , H01L21/76867 , H01L21/76886 , H01L21/76888 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlayer dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.
摘要翻译：描述了用于改变金属互连的顶表面的方法和装置。在本发明的一个实施例中，将金属互连和阻挡层形成为层间电介质（ILD），并将金属互连和阻挡层平面化到ILD的顶部。金属互连，阻挡层和ILD的顶表面用第二金属改变以形成电迁移屏障。在本发明的一个实施例中，防止了第二金属污染金属互连的电阻率。

3. 发明授权

US08299617B2 Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects 有权
标题翻译：用于形成用于集成电路互连的金属 - 金属氧化物蚀刻停止/屏障的方法和装置
公开(公告)号：US08299617B2
公开(公告)日：2012-10-30
申请号：US12763038
申请日：2010-04-19
申请人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
发明人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
IPC分类号： H01L29/40
CPC分类号： H01L21/76849 , H01L21/76829 , H01L21/76834 , H01L21/76855 , H01L21/76888 , H01L21/76897 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
摘要翻译：描述了用于与金属 - 金属氧化物电迁移屏障和蚀刻停止形成互连的方法和装置。在本发明的一个实施例中，该方法包括在平坦化的互连层的顶部上沉积金属层，所述互连层具有层间电介质（ILD），其顶部与导电互连的顶部是平面的。在本发明的一个实施方案中，该方法包括使金属层与ILD反应以在ILD的顶部形成金属氧化物层。同时，金属层不会被导电互连显着地氧化，从而在导电互连上形成金属阻挡层以改善电迁移性能。金属屏障和金属氧化物层一起包括保护层。随后可以在保护层上形成第二ILD，并且保护层可以在随后的第二ILD蚀刻期间进行蚀刻停止。

4. 发明申请

US20100219529A1 METHOD AND APPARATUS FOR FORMING METAL-METAL OXIDE ETCH STOP/BARRIER FOR INTEGRATED CIRCUIT INTERCONNECTS 有权
标题翻译：用于形成用于集成电路互连的金属氧化物蚀刻停止/障碍物的方法和装置
公开(公告)号：US20100219529A1
公开(公告)日：2010-09-02
申请号：US12763038
申请日：2010-04-19
申请人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
发明人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
IPC分类号： H01L23/532
CPC分类号： H01L21/76849 , H01L21/76829 , H01L21/76834 , H01L21/76855 , H01L21/76888 , H01L21/76897 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
摘要翻译：描述了用于与金属 - 金属氧化物电迁移屏障和蚀刻停止形成互连的方法和装置。在本发明的一个实施例中，该方法包括在平坦化的互连层的顶部上沉积金属层，所述互连层具有层间电介质（ILD），其顶部与导电互连的顶部是平面的。在本发明的一个实施方案中，该方法包括使金属层与ILD反应以在ILD的顶部形成金属氧化物层。同时，金属层不会被导电互连显着地氧化，从而在导电互连上形成金属阻挡层以改善电迁移性能。金属屏障和金属氧化物层一起包括保护层。随后可以在保护层上形成第二ILD，并且保护层可以在随后的第二ILD蚀刻期间进行蚀刻停止。

5. 发明授权

US07339271B2 Metal-metal oxide etch stop/barrier for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的金属 - 金属氧化物蚀刻停止/屏障
公开(公告)号：US07339271B2
公开(公告)日：2008-03-04
申请号：US10861657
申请日：2004-06-03
申请人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
发明人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
IPC分类号： H01L23/52
CPC分类号： H01L21/76849 , H01L21/76829 , H01L21/76834 , H01L21/76855 , H01L21/76888 , H01L21/76897 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
摘要翻译：描述了用于与金属 - 金属氧化物电迁移屏障和蚀刻停止形成互连的方法和装置。在本发明的一个实施例中，该方法包括在平坦化的互连层的顶部上沉积金属层，所述互连层具有层间电介质（ILD），其顶部与导电互连的顶部是平面的。在本发明的一个实施方案中，该方法包括使金属层与ILD反应以在ILD的顶部形成金属氧化物层。同时，金属层不会被导电互连显着地氧化，从而在导电互连上形成金属阻挡层以改善电迁移性能。金属屏障和金属氧化物层一起包括保护层。随后可以在保护层上形成第二ILD，并且保护层可以在随后的第二ILD蚀刻期间进行蚀刻停止。

6. 发明授权

US07122481B2 Sealing porous dielectrics with silane coupling reagents 失效
标题翻译：用硅烷偶联剂密封多孔电介质
公开(公告)号：US07122481B2
公开(公告)日：2006-10-17
申请号：US10627838
申请日：2003-07-25
申请人： Grant Kloster , Chih-I Wu , Xiaorong Morrow
发明人： Grant Kloster , Chih-I Wu , Xiaorong Morrow
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L21/76831 , H01L21/3105 , H01L21/31058 , H01L21/76807 , H01L21/76826
摘要： A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.
摘要翻译：本文描述了使用硅烷偶联剂密封多孔电介质的方法和结构。至少由硅，碳，氧和氢形成密封剂链（硅烷偶联剂）并暴露于多孔电介质材料，其中密封剂链与至少具有氧并且存在于多孔中的第二链反应电介质限定孔，以在多孔电介质的表面上形成连续层。

7. 发明授权

US06448177B1 Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure 有权
标题翻译：制造具有与支撑结构间隔开的双镶嵌互连的半导体器件的方法
公开(公告)号：US06448177B1
公开(公告)日：2002-09-10
申请号：US09819881
申请日：2001-03-27
申请人： Patrick Morrow , Xiaorong Morrow
发明人： Patrick Morrow , Xiaorong Morrow
IPC分类号： H01L21331
CPC分类号： H01L21/76808 , H01L21/76811 , H01L21/76814 , H01L21/7682 , H01L21/76835 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive line, and an insulating layer that is formed on the support structure and the conductive line. In the method for forming that device, a support structure is formed on a substrate, and an insulating layer is formed adjacent to it. Portions of the insulating layer are removed to form a via and a trench, which are filled with a conductive material to generate a dual damascene interconnect that includes a conductive line, wherein the conductive line is spaced from the support structure.
摘要翻译：对半导体装置及其制造方法进行说明。该半导体器件包括包括导电线的双镶嵌互连。该装置还包括与导电线隔开的支撑结构以及形成在支撑结构和导电线上的绝缘层。在用于形成该器件的方法中，在衬底上形成支撑结构，并且在其附近形成绝缘层。去除绝缘层的一部分以形成通孔和沟槽，沟槽填充有导电材料以产生包括导线的双镶嵌互连，其中导电线与支撑结构间隔开。

8. 发明授权

US07456490B2 Sealing porous dielectrics with silane coupling reagents 失效
标题翻译：用硅烷偶联剂密封多孔电介质
公开(公告)号：US07456490B2
公开(公告)日：2008-11-25
申请号：US11516410
申请日：2006-09-05
申请人： Grant Kloster , Chih-I Wu , Xiaorong Morrow
发明人： Grant Kloster , Chih-I Wu , Xiaorong Morrow
IPC分类号： H01L23/58 , H01L23/48 , H01L23/52
CPC分类号： H01L21/76831 , H01L21/3105 , H01L21/31058 , H01L21/76807 , H01L21/76826
摘要： A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.
摘要翻译：本文描述了使用硅烷偶联剂密封多孔电介质的方法和结构。至少由硅，碳，氧和氢形成密封剂链（硅烷偶联剂）并暴露于多孔电介质材料，其中密封剂链与至少具有氧并且存在于多孔中的第二链反应电介质限定孔，以在多孔电介质的表面上形成连续层。

9. 发明申请

US20070066079A1 Sealing porous dielectrics with silane coupling reagents 失效
标题翻译：用硅烷偶联剂密封多孔电介质
公开(公告)号：US20070066079A1
公开(公告)日：2007-03-22
申请号：US11516410
申请日：2006-09-05
申请人： Grant Kloster , Chih-I Wu , Xiaorong Morrow
发明人： Grant Kloster , Chih-I Wu , Xiaorong Morrow
IPC分类号： H01B13/00 , H01L21/302 , H01L29/00
CPC分类号： H01L21/76831 , H01L21/3105 , H01L21/31058 , H01L21/76807 , H01L21/76826
摘要： A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.
摘要翻译：本文描述了使用硅烷偶联剂密封多孔电介质的方法和结构。至少由硅，碳，氧和氢形成密封剂链（硅烷偶联剂）并暴露于多孔电介质材料，其中密封剂链与至少具有氧并且存在于多孔中的第二链反应电介质限定孔，以在多孔电介质的表面上形成连续层。

10. 发明申请

US20050020074A1 Sealing porous dielectrics with silane coupling reagents 失效
标题翻译：用硅烷偶联剂密封多孔电介质
公开(公告)号：US20050020074A1
公开(公告)日：2005-01-27
申请号：US10627838
申请日：2003-07-25
申请人： Grant Kloster , Chih-I Wu , Xiaorong Morrow
发明人： Grant Kloster , Chih-I Wu , Xiaorong Morrow
IPC分类号： H01L21/302 , H01L21/3105 , H01L21/461 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/3105 , H01L21/31058 , H01L21/76807 , H01L21/76826
摘要： A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.
摘要翻译：本文描述了使用硅烷偶联剂密封多孔电介质的方法和结构。至少由硅，碳，氧和氢形成密封剂链（硅烷偶联剂）并暴露于多孔电介质材料，其中密封剂链与至少具有氧并且存在于多孔中的第二链反应电介质限定孔，以在多孔电介质的表面上形成连续层。

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