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    • 5. 发明授权
    • Manufacturable GaAs VFET process
    • 可制造的GaAs VFET工艺
    • US06309918B1
    • 2001-10-30
    • US09157430
    • 1998-09-21
    • Jenn-Hwa HuangBenjamin W. GableKurt EisenbeiserDavid Rhine
    • Jenn-Hwa HuangBenjamin W. GableKurt EisenbeiserDavid Rhine
    • H01L21338
    • H01L29/66856H01L29/8122Y10S438/945
    • A manufacturable GaAs VFET process includes providing a doped GaAs substrate with a lightly doped first epitaxial layer thereon and a heavily doped second epitaxial layer positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of elongated, spaced apart source areas. Using the patterned conductive layer, a plurality of gate trenches are etched into the first epitaxial layer adjacent the source areas. The bottoms of the gate trenches are implanted and activated to form gate areas. A gate contact is deposited in communication with the implanted gate areas, a source contact is deposited in communication with the patterned conductive layer overlying the source areas, and a drain contact is deposited on the rear surface of the substrate.
    • 可制造的GaAs VFET工艺包括在其上提供掺杂的GaAs衬底和其上的轻掺杂的第一外延层和位于第一外延层上的重掺杂的第二外延层。 耐温导电层定位在第二外延层上并且被图案化以限定多个细长的间隔开的源极区域。 使用图案化的导电层,多个栅极沟槽被蚀刻到与源极区域相邻的第一外延层中。 栅极沟槽的底部被植入和激活以形成栅极区域。 栅极接触被沉积成与植入的栅极区域连通,源极接触层沉积成与覆盖在源极区域上的图案化导电层连通,并且漏极接触沉积在衬底的后表面上。