专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09041153B2 MIM capacitor having a local interconnect metal electrode and related structure 有权
标题翻译：具有局部互连金属电极和相关结构的MIM电容器
公开(公告)号：US09041153B2
公开(公告)日：2015-05-26
申请号：US13248823
申请日：2011-09-29
申请人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
发明人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
IPC分类号： H01L29/92 , H01L23/522 , H01L49/02
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.
摘要翻译：根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器形成在底部电容器电极上的层间势垒电介质上的电极。顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。在一个实施例中，底部电容器电极由栅极金属形成。该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

2. 发明申请

US20130082351A1 Method for Fabricating a MIM Capacitor Having a Local Interconnect Metal Electrode and Related Structure 有权
标题翻译：具有局部互连金属电极和相关结构的MIM电容器的制造方法
公开(公告)号：US20130082351A1
公开(公告)日：2013-04-04
申请号：US13248823
申请日：2011-09-29
申请人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
发明人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.
摘要翻译：根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器形成在底部电容器电极上的层间势垒电介质上的电极。顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。在一个实施例中，底部电容器电极由栅极金属形成。该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

3. 发明授权

US08748277B2 Method for fabricating a MOS transistor with reduced channel length variation 有权
标题翻译：具有减小的沟道长度变化的MOS晶体管的制造方法
公开(公告)号：US08748277B2
公开(公告)日：2014-06-10
申请号：US13613520
申请日：2012-09-13
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

4. 发明申请

US20130017658A1 Method for Fabricating a MOS Transistor with Reduced Channel Length Variation 有权
标题翻译：制造具有减少通道长度变化的MOS晶体管的方法
公开(公告)号：US20130017658A1
公开(公告)日：2013-01-17
申请号：US13613520
申请日：2012-09-13
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

5. 发明授权

US08269275B2 Method for fabricating a MOS transistor with reduced channel length variation and related structure 有权
标题翻译：具有减小沟道长度变化和相关结构的MOS晶体管的制造方法
公开(公告)号：US08269275B2
公开(公告)日：2012-09-18
申请号：US12589357
申请日：2009-10-21
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

6. 发明授权

US08659081B2 Transistor with reduced channel length variation 有权
标题翻译：具有减小通道长度变化的晶体管
公开(公告)号：US08659081B2
公开(公告)日：2014-02-25
申请号：US13613864
申请日：2012-09-13
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

7. 发明申请

US20130001687A1 Transistor with Reduced Channel Length Variation 有权
标题翻译：具有减少通道长度变化的晶体管
公开(公告)号：US20130001687A1
公开(公告)日：2013-01-03
申请号：US13613864
申请日：2012-09-13
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

8. 发明申请

US20110089490A1 Method for fabricating a MOS transistor with reduced channel length variation and related structure 有权
标题翻译：具有减小沟道长度变化和相关结构的MOS晶体管的制造方法
公开(公告)号：US20110089490A1
公开(公告)日：2011-04-21
申请号：US12589357
申请日：2009-10-21
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

9. 发明申请

US20100284210A1 One-time programmable memory cell 审中-公开
标题翻译：一次性可编程存储单元
公开(公告)号：US20100284210A1
公开(公告)日：2010-11-11
申请号：US12387573
申请日：2009-05-05
申请人： Henry Kuo-Shun Chen , Xiangdong Chen , Wei Xia
发明人： Henry Kuo-Shun Chen , Xiangdong Chen , Wei Xia
IPC分类号： G11C17/00
CPC分类号： G11C17/16
摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a cell transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The cell transistor has a source, a gate, and a body shorted together. A programming operation causes a punchthrough to occur between the source and a drain of the cell transistor in response to a programming voltage on the bitline and the wordline. A channel length of the cell transistor is substantially less than a channel length of the access transistor. In one embodiment, the access transistor is an NFET while the cell transistor is a PFET. In another embodiment, the access transistor is an NFET and the cell transistor is also an NFET. Various embodiments result in a reduction of the required programming voltage.
摘要翻译：根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的单元晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。单元晶体管具有源极，栅极和与之短接在一起的主体。响应于位线和字线上的编程电压，编程操作导致在单元晶体管的源极和漏极之间发生穿透。单元晶体管的沟道长度基本上小于存取晶体管的沟道长度。在一个实施例中，存取晶体管是NFET，而单元晶体管是PFET。在另一个实施例中，存取晶体管是NFET，单元晶体管也是NFET。各种实施例导致所需编程电压的降低。

10. 发明授权

US09129856B2 Method for efficiently fabricating memory cells with logic FETs and related structure 有权
标题翻译：用逻辑FET和相关结构有效地制造存储单元的方法
公开(公告)号：US09129856B2
公开(公告)日：2015-09-08
申请号：US13179248
申请日：2011-07-08
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： H01L27/115 , H01L21/8238
CPC分类号： H01L27/11534 , H01L21/823842
摘要： According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common substrate in the memory and logic regions. The method also includes forming a polysilicon segment over the lower dielectric segment in the memory region, while concurrently forming a sacrificial polysilicon segment over the lower dielectric segment in the logic region. Furthermore, the method includes removing from the logic region the lower dielectric segment and the sacrificial polysilicon segment. The method additionally includes forming a high-k segment in the logic region over the common substrate, and in the memory region over the polysilicon segment and forming a metal segment over the high-k segment in the logic and memory regions. An exemplary structure achieved by the described exemplary method is also disclosed.
摘要翻译：根据一个示例性实施例，用于同时制造具有公共衬底中的逻辑区域的存储区域的方法包括在存储器和逻辑区域中的公共衬底中形成下部介电段。该方法还包括在存储器区域中的下介电段上形成多晶硅段，同时在逻辑区域中的下介电段上同时形成牺牲多晶硅段。此外，该方法包括从逻辑区域去除下介电段和牺牲多晶硅段。该方法还包括在公共衬底上的逻辑区域中形成高k区段，并在多晶硅区段上的存储区域中形成高k区段，并在逻辑和存储区域中的高k区段上形成金属区段。还公开了通过描述的示例性方法实现的示例性结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式