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1. 发明申请

US20090156010A1 THIN FILM ETCHING METHOD AND SEMICONDUCTOR DEVICE FABRICATION USING SAME 有权
标题翻译：薄膜蚀刻方法和使用相同的半导体器件制造
公开(公告)号：US20090156010A1
公开(公告)日：2009-06-18
申请号：US11959034
申请日：2007-12-18
申请人： Xiang Hu , Hai Cong , Pradeep Yelehanka , Mei Sheng Zhou
发明人： Xiang Hu , Hai Cong , Pradeep Yelehanka , Mei Sheng Zhou
IPC分类号： H01L21/302
CPC分类号： H01J37/32963 , H01J37/32935
摘要： A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.
摘要翻译：一种用于蚀刻薄膜并制造半导体器件的方法包括：在监测从基板远离的端点检测层的移除的同时，对衬底上的薄膜进行蚀刻，从而通过监测薄膜蚀刻来精确控制薄膜蚀刻移除端点检测层。端点检测层形成在暴露于与要蚀刻的薄膜相同的蚀刻条件的蚀刻装置的表面上。当从蚀刻装置的表面去除预定量的端点检测层时，停止对薄膜的蚀刻。

2. 发明授权

US07879732B2 Thin film etching method and semiconductor device fabrication using same 有权
标题翻译：薄膜蚀刻方法和使用其的半导体器件制造
公开(公告)号：US07879732B2
公开(公告)日：2011-02-01
申请号：US11959034
申请日：2007-12-18
申请人： Xiang Hu , Hai Cong , Pradeep Yelehanka , Mei Sheng Zhou
发明人： Xiang Hu , Hai Cong , Pradeep Yelehanka , Mei Sheng Zhou
IPC分类号： H01L21/302 , G01R31/00 , B44C1/22
CPC分类号： H01J37/32963 , H01J37/32935
摘要： A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.
摘要翻译：一种用于蚀刻薄膜并制造半导体器件的方法包括：在监测从基板远离的端点检测层的移除的同时，对衬底上的薄膜进行蚀刻，从而通过监测薄膜蚀刻来精确控制薄膜蚀刻移除端点检测层。端点检测层形成在暴露于与要蚀刻的薄膜相同的蚀刻条件的蚀刻装置的表面上。当从蚀刻装置的表面去除预定量的端点检测层时，停止对薄膜的蚀刻。

3. 发明授权

US08546873B2 Integrated circuit and method of fabrication thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08546873B2
公开(公告)日：2013-10-01
申请号：US13241215
申请日：2011-09-23
申请人： Jinping Liu , Hai Cong , Binbin Zhou , Alex Kh See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Hai Cong , Binbin Zhou , Alex Kh See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L29/66
CPC分类号： H01L21/823468 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
摘要翻译：一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。

4. 发明授权

US08058123B2 Integrated circuit and method of fabrication thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08058123B2
公开(公告)日：2011-11-15
申请号：US11946843
申请日：2007-11-29
申请人： Jinping Liu , Hai Cong , Binbin Zhou , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Hai Cong , Binbin Zhou , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/823468 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
摘要翻译：一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。

5. 发明授权

US07745320B2 Method for reducing silicide defects in integrated circuits 有权
标题翻译：降低集成电路中硅化物缺陷的方法
公开(公告)号：US07745320B2
公开(公告)日：2010-06-29
申请号：US12124177
申请日：2008-05-21
申请人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L29/00 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

6. 发明授权

US08394724B2 Processing with reduced line end shortening ratio 有权
标题翻译：处理缩短了线端缩短率
公开(公告)号：US08394724B2
公开(公告)日：2013-03-12
申请号：US11843629
申请日：2007-08-22
申请人： Hai Cong , Wei Loong Loh , Krishan Gopal , Xin Zhang , Mei Sheng Zhou , Pradeep Ramachandramurthy Yelehanka
发明人： Hai Cong , Wei Loong Loh , Krishan Gopal , Xin Zhang , Mei Sheng Zhou , Pradeep Ramachandramurthy Yelehanka
IPC分类号： H01L21/312
CPC分类号： H01L21/32137 , H01L21/32139
摘要： A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.
摘要翻译：用于形成具有减少的线端缩短（LES）的器件特征的方法包括修整器件特征以在蚀刻期间实现期望的子接地规则临界尺寸以形成器件特征。

7. 发明授权

US07960283B2 Method for reducing silicide defects in integrated circuits 有权
标题翻译：降低集成电路中硅化物缺陷的方法
公开(公告)号：US07960283B2
公开(公告)日：2011-06-14
申请号：US12825325
申请日：2010-06-28
申请人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

8. 发明授权

US08324011B2 Implementation of temperature-dependent phase switch layer for improved temperature uniformity during annealing 有权
标题翻译：实现温度相关的开关层，以提高退火过程中的温度均匀性
公开(公告)号：US08324011B2
公开(公告)日：2012-12-04
申请号：US11853156
申请日：2007-09-11
申请人： Chyiu Hyia Poon , Alex See , Mei Sheng Zhou
发明人： Chyiu Hyia Poon , Alex See , Mei Sheng Zhou
IPC分类号： H01L21/00
CPC分类号： H01L21/324 , H01L21/268
摘要： The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.
摘要翻译：本发明提供了一种通过向半导体结构施加温度相关的相位开关层来退火半导体的方法。温度相关的相位开关层在预定温度下将相从非晶形变化为结晶。当半导体结构退火时，电磁辐射在到达半导体结构之前通过温度相关的相位开关层。当达到期望的退火温度时，温度相关的相位开关层基本上阻止电磁辐射到达半导体结构。结果，半导体在晶片上以一致的温度退火。温度相关的相位开关层改变相位的温度可以通过离子注入工艺来控制。

9. 发明申请

US20110281410A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL CHANNEL AND TRANSISTOR HAVING SAME 有权
标题翻译：用于制造具有外延通道的半导体器件和具有其的晶体管的方法
公开(公告)号：US20110281410A1
公开(公告)日：2011-11-17
申请号：US13190805
申请日：2011-07-26
申请人： JINPING LIU , Alex KH See , Mei Sheng Zhou , Liang Choo Hsia
发明人： JINPING LIU , Alex KH See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/4958 , H01L29/4975 , H01L29/51 , H01L29/66545 , H01L29/66651 , H01L29/7848
摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
摘要翻译：具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。外延材料限于开口，从而形成外延沟道。在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

10. 发明授权

US08012839B2 Method for fabricating a semiconductor device having an epitaxial channel and transistor having same 有权
标题翻译：用于制造具有外延沟道的半导体器件的方法和具有其的晶体管
公开(公告)号：US08012839B2
公开(公告)日：2011-09-06
申请号：US12040562
申请日：2008-02-29
申请人： Jinping Liu , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/4958 , H01L29/4975 , H01L29/51 , H01L29/66545 , H01L29/66651 , H01L29/7848
摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
摘要翻译：具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。外延材料限于开口，从而形成外延沟道。在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

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