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1. 发明申请

US20110281139A1 Wastewater Treatment Process and Device for Electricity Generation and Desalination Simultaneously 审中-公开
标题翻译：污水处理工艺和发电和脱盐装置同时进行
公开(公告)号：US20110281139A1
公开(公告)日：2011-11-17
申请号：US13145987
申请日：2009-01-23
申请人： Xia Huang , Xiaoxin Cao , Peng Liang , Kang Xiao , Yingjun Zhou , Bruce Logan
发明人： Xia Huang , Xiaoxin Cao , Peng Liang , Kang Xiao , Yingjun Zhou , Bruce Logan
IPC分类号： H01M8/16 , C02F1/469
CPC分类号： C02F1/469 , B01D61/44 , B01D61/46 , C02F1/4693 , C02F3/005 , Y02A20/134
摘要： A wastewater treatment process and wastewater treatment device for generating current and desalting simultaneously are provided. The device may comprise an anode compartment, an anion exchange membrane, a middle desalting compartment, a cation exchange membrane and a cathode compartment. Wastewater flows into the anode compartment, and is oxidized under the action of an electricigenic microbe. In the desalting compartment, anions are transferred to the anode compartment through the anion exchange membrane, and cations are transferred to the cathode compartment through the cation exchange membrane, thus achieving a desalting process and forming an internal current. Electrons are transferred to the cathode through an external circuit such that a reduction reaction takes place and a current generation is achieved. The wastewater treatment, the current generation and the desalination are achieved simultaneously in the process.
摘要翻译：提供了一种用于同时产生电流和脱盐的废水处理过程和废水处理装置。该装置可以包括阳极室，阴离子交换膜，中间脱盐室，阳离子交换膜和阴极室。废水流入阳极室，并在发电微生物的作用下被氧化。在脱盐室中，阴离子通过阴离子交换膜转移到阳极室，阳离子通过阳离子交换膜转移到阴极室，从而实现脱盐过程并形成内部电流。电子通过外部电路转移到阴极，使得发生还原反应并实现电流产生。在此过程中同时实现废水处理，当代和淡化。

2. 发明授权

US08913706B2 Multi-channel multi-protocol transceiver with independent channel configuration using single frequency reference clock source 有权
标题翻译：具有独立通道配置的多通道多协议收发器，采用单频参考时钟源
公开(公告)号：US08913706B2
公开(公告)日：2014-12-16
申请号：US12860596
申请日：2010-08-20
申请人： Jun Cao , Afshin Momtaz , Chung-Jue Chen , Kang Xiao , Vivek Telang , Ali Ghiasi
发明人： Jun Cao , Afshin Momtaz , Chung-Jue Chen , Kang Xiao , Vivek Telang , Ali Ghiasi
IPC分类号： H03D3/24
CPC分类号： H03L7/18
摘要： A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider.
摘要翻译：一种用于从单个恒定输入参考时钟频率产生多个输出时钟频率之一的电路。该电路包括参考时钟系统和锁相环。参考时钟系统包括旁路路径，包括第一整数除法器的分频器路径和多路复用器。第一整数分频器的除数基于一组可能的通信协议的所选通信协议。多路复用器被配置为基于所选择的通信协议来路由旁路路径或分路器路径。锁相环包括压控振荡器和反馈路径。反馈路径包括第二整数分频器。第二整数分频器的除数基于所选择的通信协议。参考时钟系统被配置为接收恒定的参考时钟频率。压控振荡器被配置为产生与所选择的通信协议相对应的多个输出时钟频率中的一个。所选择的输出时钟频率基于多路复用器的路由，第一整数除法器的除数和第二整数除法器的除数中的至少一个来产生。

3. 发明授权

US08341509B2 Forward error correction (FEC) scheme for communications 有权
标题翻译：用于通信的前向纠错（FEC）方案
公开(公告)号：US08341509B2
公开(公告)日：2012-12-25
申请号：US12725887
申请日：2010-03-17
申请人： Zhongfeng Wang , Chung-Jue Chen , Kang Xiao
发明人： Zhongfeng Wang , Chung-Jue Chen , Kang Xiao
IPC分类号： G06F11/00
CPC分类号： H03M13/2909 , H03M13/152 , H03M13/253 , H03M13/2903
摘要： Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits. In addition, interleaving may be performing at various stages of the encoding processing.
摘要翻译：用于通信的前向纠错（FEC）方案。信息比特序列的比特的适当选择/排列经历一种或多种类型的后续编码，以生成可以随后经历适当处理以生成在通信信道内启动的连续时间信号的编码比特序列。在一些实施例中，信息比特序列在被划分成多个信息比特组之后，首先经历第一编码模块内的第一编码，从而生成多个冗余/奇偶校验比特组（例如，每个冗余/奇偶校验位组对应于一个信息位组）。然后，在执行冗余/奇偶校验位组和信息位组内的位的任何期望和适当的选择/布置之后，在其上执行第二编码模块内的第二编码以产生附加的冗余/奇偶校验位。此外，可以在编码处理的各个阶段执行交织。

4. 发明申请

US20080130679A1 TRANSCEIVER SYSTEM AND METHOD SUPPORTING VARIABLE RATES AND MULTIPLE PROTOCOLS 审中-公开
标题翻译：收支系统和支持可变利率和多项协议的方法
公开(公告)号：US20080130679A1
公开(公告)日：2008-06-05
申请号：US11933881
申请日：2007-11-01
申请人： Vikram Natarajan , Kang Xiao , Mario Caresosa , Jay Proano , David Chung , Afshin Momtaz , Randy Stolaruk , Xin Wang , Namik Kocaman
发明人： Vikram Natarajan , Kang Xiao , Mario Caresosa , Jay Proano , David Chung , Afshin Momtaz , Randy Stolaruk , Xin Wang , Namik Kocaman
IPC分类号： H04J3/16 , H04J3/22 , H04B10/00 , H04J14/00
CPC分类号： H04Q11/0478 , H04J3/04 , H04J3/0685 , H04J3/1611 , H04J2203/0046 , H04J2203/0067 , H04J2203/0082 , H04J2203/0089 , Y10S370/907
摘要： Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.
摘要翻译：本发明是一种多速率收发器，其中可以以第一数据速率接收数据并以第二数据速率发送数据。收发器装置包括用于以一个数据速率接收能够将数据从第一速率映射到第二速率的映射器的数据的第一接口和用于以第二数据速率发送数据的第二接口。

5. 发明授权

US07356076B2 System and method supporting auto-recovery in a transceiver system 有权
标题翻译：支持收发系统自动恢复的系统和方法
公开(公告)号：US07356076B2
公开(公告)日：2008-04-08
申请号：US10313258
申请日：2002-12-05
申请人： Kang Xiao , Mario Caresosa , Hongtao Jiang , Randall Stolaruk
发明人： Kang Xiao , Mario Caresosa , Hongtao Jiang , Randall Stolaruk
IPC分类号： H04B1/38
CPC分类号： H04J3/0685 , H04J3/04 , H04J3/0688 , H04J2203/0089
摘要： A method and apparatus are disclosed to aid a transceiver chip, in a serial data communications system, in recovering from a system-side, out-bound data clocking problem. If a problem with a primary clock signal, used to clock data from a system-side of a transceiver chip through at least a part of an out-bound data path of the transceiver chip, is detected, then a more reliable secondary clock signal is substituted for the primary clock signal. Once it is determined that the primary clock signal has recovered, the primary clock signal is switched back to and certain discrete circuits of the out-bound data path of the transceiver chip are automatically reset in hardware without the need for system level intervention to avoid any problems due to clock glitches on the primary clock signal during the switching.
摘要翻译：公开了一种方法和装置，用于帮助串行数据通信系统中的收发器芯片从系统侧的出站数据计时问题中恢复。如果检测到用于通过收发器芯片的出站数据路径的至少一部分对收发器芯片的系统侧的数据进行时钟的主时钟信号的问题，则更可靠的辅助时钟信号是代替主时钟信号。一旦确定主时钟信号已恢复，则主时钟信号被切换回并且收发器芯片的出站数据路径中的某些离散电路在硬件中自动重置，而不需要系统级干预来避免任何在切换期间由于时钟信号引起的主时钟信号引起的问题。

6. 发明申请

US20120179949A1 METHOD AND SYSTEM FOR ENCODING FOR 100G-KR NETWORKING 有权
标题翻译：用于编码100G-KR网络的方法和系统
公开(公告)号：US20120179949A1
公开(公告)日：2012-07-12
申请号：US13345274
申请日：2012-01-06
申请人： Zhongfeng Wang , Hongtao Jiang , Chung-Jue Chen , Kang Xiao
发明人： Zhongfeng Wang , Hongtao Jiang , Chung-Jue Chen , Kang Xiao
IPC分类号： H04J3/00 , G06F11/10 , H03M13/05
CPC分类号： H04L1/0041 , H03M13/1515 , H03M13/175 , H03M13/27 , H03M13/2778 , H04L1/0057 , H04L1/0071 , H04L25/4908
摘要： In one embodiment, a coding method that uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving.
摘要翻译：在一个实施例中，一种基于给定代码转换方法使用某些前向纠错码并根据突发交织传送代码的编码方法。

7. 发明授权

US07486121B2 System and method for generating two effective frequencies using a single clock 有权
标题翻译：使用单个时钟产生两个有效频率的系统和方法
公开(公告)号：US07486121B2
公开(公告)日：2009-02-03
申请号：US10938467
申请日：2004-09-09
申请人： Kang Xiao , Steve Thomas , Robert Holder , Timothy Chan
发明人： Kang Xiao , Steve Thomas , Robert Holder , Timothy Chan
IPC分类号： H03K5/01 , G01R31/28
CPC分类号： H03K5/00006 , H03K5/156
摘要： A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. When the count value reaches a predetermined blanking value, a blanking signal is generated. The blanking signal blanks at least one clock pulse of the first clock signal. The process is repeated multiple times at a predetermined rate corresponding to the predetermined blanking value to generate the second clock signal.
摘要翻译：公开了一种用于从具有第一有效时钟频率的第一时钟信号产生具有第二有效时钟频率的第二时钟信号的方法和装置。对第一时钟信号的时钟脉冲进行计数以产生计数值。当计数值达到预定的消隐值时，产生消隐信号。消隐信号使第一时钟信号的至少一个时钟脉冲空白。该过程以对应于预定消隐值的预定速率重复多次以产生第二时钟信号。

8. 发明授权

US06327641B1 Method of implementing a geometry per wedge (GPW) based headerless solution in a disk drive formatter and a computer program product incorporating the same 失效
标题翻译：在磁盘驱动器格式化程序中实现基于楔形几何（GPW）的无头解决方案的方法和包含该几何的计算机程序产品
公开(公告)号：US06327641B1
公开(公告)日：2001-12-04
申请号：US09052146
申请日：1998-03-31
申请人： Kang Xiao , Dennis Keats , Andrew Yanowitz
发明人： Kang Xiao , Dennis Keats , Andrew Yanowitz
IPC分类号： G06F1200
CPC分类号： G06F3/0608 , G06F3/064 , G06F3/0658 , G06F3/0674 , G11B5/59633 , G11B20/10 , G11B20/1217 , G11B2020/1062 , G11B2020/1232 , G11B2020/1287 , G11B2220/2537 , G11B2220/255
摘要： A method of implementing a geometry per wedge (GPW) based headerless solution in a disk drive formatter having a corresponding memory buffer. The disk drive formatter includes high and low processing engines and formats a data storage disk. The method includes the step of processing a command instruction, which instructs the high-level processing engine to execute a disk operation with respect to a predetermined sector. The method also includes the steps of searching for the predetermined sector using sector layout information derived from a GPW table including entries which define the relative position of sector pulses on a track within a data wedge of the disk, and transferring the predetermined sector from the disk to the buffer memory.
摘要翻译：在具有对应的存储器缓冲器的磁盘驱动器格式化器中实现基于楔形几何（GPW）的无头解决方案。磁盘驱动器格式器包括高和低处理引擎，并格式化数据存储磁盘。该方法包括处理命令指令的步骤，该命令指令指示高级处理引擎相对于预定扇区执行盘操作。该方法还包括以下步骤：使用从GPW表导出的扇区布局信息来搜索预定扇区，所述扇区布局信息包括限定盘的数据楔内的轨道上的扇区脉冲的相对位置的条目，以及从盘的传输预定扇区到缓冲存储器。

9. 发明授权

US6167461A Programmable high performance disk formatter for headerless disk drive controller executing a series of low level instructions generated by a high level processing engine 失效
标题翻译：用于无头盘驱动器控制器的可编程高性能磁盘格式化器，执行由高级处理引擎生成的一系列低级指令
公开(公告)号：US6167461A
公开(公告)日：2000-12-26
申请号：US52145
申请日：1998-03-31
申请人： Dennis Keats , Kang Xiao
发明人： Dennis Keats , Kang Xiao
IPC分类号： G06F3/06 , G11B5/596 , G06F13/10 , G06F9/22
CPC分类号： G06F3/0607 , G06F3/0638 , G06F3/0676 , G11B5/59633
摘要： A programmable disk formatter for a disk controller in a headerless hard disk drive (HDD) system is disclosed. The disk formatter includes a high level processing engine that generates on the fly low level instructions that are executed by a low level processing engine. The disk formatter also includes a servo interface for interfacing the disk formatter to the servo timing logic, sector direct memory access (SDMA), and a QT/SP interface for interfacing the disk formatter to other processors in the disk controller, such as a system processor (SP) or Q-transmogrifier (QT) processor. The high level engine and low level engine operate semi-independently. The former processes SP- or QT-converted host computer commands in such a fashion that the low level instructions are generated and passed by the high level engine in time for the low level engine to execute them in coordination with the disk data rate. The high level engine is programmable with a high level instruction set, assembly language in the preferred embodiment, so that different drive formats can be accommodated with only software changes involving reprogramming of the high level engine and certain tracking/geometry tables stored in memory. The architecture and logic of the disk controller render a highly flexible, easily programmable. user friendly solution to the problem that disk controller designers face in accommodating each new generation of magnetic disks and each new approach to formatting.
摘要翻译：公开了一种用于无头硬盘驱动器（HDD）系统中的盘控制器的可编程磁盘格式器。磁盘格式器包括一个由低级处理引擎执行的低电平指令产生的高级处理引擎。磁盘格式器还包括用于将磁盘格式化器与伺服定时逻辑，扇区直接存储器访问（SDMA）接口的伺服接口，以及用于将磁盘格式器与磁盘控制器中的其它处理器接口的QT / SP接口，例如系统处理器（SP）或Q-转换器（QT）处理器。高级发动机和低级发动机半独立运行。前者处理SP或QT转换的主计算机命令，使得低级别指令及时由高级引擎生成和传递，以使低级引擎与磁盘数据速率协调执行它们。高级引擎可以用优选实施例中的高级指令集，汇编语言来编程，使得仅仅涉及重新编程高级引擎和存储在存储器中的某些跟踪/几何表的软件变化可以适应不同的驱动器格式。磁盘控制器的架构和逻辑提供了高度灵活性，易于编程。用户友好的解决方案，解决磁盘控制器设计人员面对的新一代磁盘和每种新的格式化方法所面临的问题。

10. 发明授权

US5909336A Position detection scheme for headerless disk controller 失效
标题翻译：无头磁盘控制器的位置检测方案
公开(公告)号：US5909336A
公开(公告)日：1999-06-01
申请号：US802293
申请日：1997-02-18
申请人： James Schaffner , Dong Cho , Kang Xiao , Mark J. Blair , Joanne Wu , Patrick Conley , Stephen Finch
发明人： James Schaffner , Dong Cho , Kang Xiao , Mark J. Blair , Joanne Wu , Patrick Conley , Stephen Finch
IPC分类号： G11B5/55 , G11B5/596 , G11B21/08
CPC分类号： G11B21/083 , G11B5/5534 , G11B5/5543 , G11B5/59655 , G11B5/59688
摘要： The present invention provides a method and apparatus for providing position detection using a unique binary sequence encoded in indexing bits stored in servo wedges. The present invention generates a unique binary sequence (UBS) code and stores the bits of such a code in the indexing bits of the servo wedges. The bits are read from the servo wedges and used to provide unique identification of head position. Each servo wedge and each data field can be uniquely identified, even servo wedges and data fields under different heads. The present invention may be used to provide initial position detection, position verification during normal operation, and position verification upon head switching. When used for position verification, the present invention uses a confidence block to determine the confidence level with which the head is believed to be correctly positioned. One or more programmable thresholds may be used to qualify operations such as reading information from a disk, writing information to a disk, or seeking a location on a disk. If these thresholds are not met for the corresponding operations, the initial position detection capability of the present invention may be used to provide position recovery.
摘要翻译：本发明提供一种使用在存储在伺服楔中的索引位中编码的唯一二进制序列来提供位置检测的方法和装置。本发明生成唯一的二进制序列（UBS）码，并将这种码的比特存储在伺服楔的索引位中。这些位从伺服楔中读取，用于提供头位置的唯一识别。每个伺服楔和每个数据场可以被唯一地识别，甚至伺服楔和数据场不同的头。本发明可以用于在头切换时提供初始位置检测，正常操作期间的位置验证和位置验证。当用于位置验证时，本发明使用置信区块来确定头部被认为被正确定位的置信水平。可以使用一个或多个可编程阈值来限定诸如从盘读取信息，将信息写入磁盘或寻找磁盘上的位置等操作。如果对于相应的操作不符合这些阈值，则可以使用本发明的初始位置检测能力来提供位置恢复。

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