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    • 2. 发明授权
    • Method for synchronization of peripherals with a central processing unit in an embedded system
    • 外设与嵌入式系统中的中央处理单元同步的方法
    • US08095707B2
    • 2012-01-10
    • US12194060
    • 2008-08-19
    • Xiaoqian ZhangZhiyong GuanQi Li
    • Xiaoqian ZhangZhiyong GuanQi Li
    • G06F3/00G06F5/00
    • G06F1/12
    • A method and apparatus for synchronizing I/O peripherals with a CPU in an embedded system is discussed. The method involves receiving an address from the CPU in response to a read and/or write access, translating the address received from the CPU to identify a I/O peripheral to be accessed, disabling the operation of the CPU and synchronizing a memory from the CPU clock domain to the clock domain of the identified I/O peripheral. Upon completion of the read/write access, the identified I/O peripheral sends an acknowledgment, the memory is then synchronized from the clock domain of the I/O peripheral to the CPU clock domain and the operation of the CPU is then enabled.In another embodiment, if the acknowledgement from the identified I/O peripheral is not received within a predefined time duration, reserved data is sent to the CPU and the operation/access can be restarted.
    • 讨论了嵌入式系统中的I / O外设与CPU同步的方法和装置。 该方法包括响应于读和/或写访问从CPU接收地址,翻译从CPU接收的地址以识别要访问的I / O外设,禁止CPU的操作并使来自 CPU时钟域到所识别的I / O外设的时钟域。 在完成读/写访问后,所识别的I / O外设发送确认,然后将存储器从I / O外设的时钟域同步到CPU时钟域,然后启用CPU的操作。 在另一个实施例中,如果在预定义的持续时间内未接收到来自所识别的I / O外围设备的确认,则保留的数据被发送到CPU,并且可以重新启动操作/访问。
    • 4. 发明申请
    • METHOD FOR SYNCHRONIZATION OF PERIPHERALS WITH A CENTRAL PROCESSING UNIT IN AN EMBEDDED SYSTEM
    • 嵌入式系统中央处理单元同步外设的方法
    • US20100049888A1
    • 2010-02-25
    • US12194060
    • 2008-08-19
    • XIAOQIAN ZHANGZhiyong GuanQi Li
    • XIAOQIAN ZHANGZhiyong GuanQi Li
    • G06F1/12
    • G06F1/12
    • A method and apparatus for synchronizing I/O peripherals with a CPU in an embedded system is discussed. The method involves receiving an address from the CPU in response to a read and/or write access, translating the address received from the CPU to identify a I/O peripheral to be accessed, disabling the operation of the CPU and synchronizing a memory from the CPU clock domain to the clock domain of the identified I/O peripheral. Upon completion of the read/write access, the identified I/O peripheral sends an acknowledgment, the memory is then synchronized from the clock domain of the I/O peripheral to the CPU clock domain and the operation of the CPU is then enabled.In another embodiment, if the acknowledgement from the identified I/O peripheral is not received within a predefined time duration, reserved data is sent to the CPU and the operation/access can be restarted.
    • 讨论了嵌入式系统中的I / O外设与CPU同步的方法和装置。 该方法包括响应于读和/或写访问从CPU接收地址,翻译从CPU接收的地址以识别要访问的I / O外设,禁止CPU的操作并使来自 CPU时钟域到所识别的I / O外设的时钟域。 在完成读/写访问后,所识别的I / O外设发送确认,然后将存储器从I / O外设的时钟域同步到CPU时钟域,然后启用CPU的操作。 在另一个实施例中,如果在预定义的持续时间内未接收到来自所识别的I / O外围设备的确认,则保留的数据被发送到CPU,并且可以重新启动操作/访问。
    • 9. 发明授权
    • Ultrasonic instrument and method for controlling its multiple probes
    • 超声波仪器及其多个探针的控制方法
    • US07971776B2
    • 2011-07-05
    • US12269671
    • 2008-11-12
    • Zhiyong GuanZhengpeng Fu
    • Zhiyong GuanZhengpeng Fu
    • G06F17/00
    • A61B8/00A61B8/4438
    • An ultrasonic instrument includes a socket and a front-end system, wherein the socket is provided with at least two probe model identification pins and a plurality of functional signal pins. The front-end system comprises a decoding module, a switch selection module, and a probe driving control module. The decoding module has its input terminals electrically connected to the probe model identification pins of the socket, and has its output terminal coupled to the control terminal of the switch selection module. The input terminals of the switch selection module are electrically connected to the functional signal pins of the socket respectively, and in response to a probe identification signal outputted from the decoding module to the control terminal, the switch selection module establishes connection between its input terminals and a group of output terminals corresponding to the probe identification signal. The probe driving control module is electrically connected to the output terminals of the switch selection module.
    • 超声波仪器包括插座和前端系统,其中所述插座设置有至少两个探针模型识别引脚和多个功能信号引脚。 前端系统包括解码模块,开关选择模块和探头驱动控制模块。 解码模块的输入端子电连接到插座的探头型号识别引脚,并且其输出端耦合到开关选择模块的控制端。 开关选择模块的输入端子分别电连接到插座的功能信号引脚,并且响应于从解码模块输出到控制端的探头识别信号,开关选择模块建立其输入端子与 与探头识别信号对应的一组输出端子。 探头驱动控制模块电连接到开关选择模块的输出端。