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    • 2. 发明申请
    • DUAL GATE OXIDE STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD THEREOF
    • 半导体器件中的双栅氧化物结构及其方法
    • US20070246779A1
    • 2007-10-25
    • US11769567
    • 2007-06-27
    • Jong-Sik CHUNHyun-Ho JOByung-Hong CHUNG
    • Jong-Sik CHUNHyun-Ho JOByung-Hong CHUNG
    • H01L29/78H01L21/336
    • H01L21/823481H01L21/76229H01L21/823462
    • In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of manufacturing the dual gate insulation layer includes, forming the device isolation layer so that an uppermost part thereof is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions. Whereby, it is be effective till a portion of trench sidewall utilized as the active region, to increase a cell current of the active region and to prevent a stringer caused by a stepped coverage between the active region and a field region and a dent caused on a boundary face between the active region and the field region.
    • 在制造半导体器件的双栅氧化层的方法中,其具有在半导体衬底上以相互不同的电压工作的第一和第二有源区,所述第一和第二有源区具有STI(浅沟槽隔离)的器件隔离层, 结构体; 制造双栅极绝缘层的方法包括:在形成与第一和第二有源区的上表面相对应的栅绝缘层之前,形成器件隔离层,使其最上部位于第一和第二有源区的上表面下方, 第二活跃区域。 由此,直到用作有源区域的沟槽侧壁的一部分为止,增加有源区域的单元电流并且防止由有源区域和场区域之间的阶梯式覆盖引起的桁条以及由 活动区域和场区域之间的边界面。