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    • 3. 发明申请
    • METHOD OF MANUFACTURING THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR SUBSTRATE
    • 制造薄膜晶体管和薄膜晶体管基板的方法
    • US20100140706A1
    • 2010-06-10
    • US12507725
    • 2009-07-22
    • Jae Bon KOOIn-Kyu YouSeongdeok AhnKyoung Ik Cho
    • Jae Bon KOOIn-Kyu YouSeongdeok AhnKyoung Ik Cho
    • H01L29/786H01L21/336
    • H01L29/78603H01L27/1266H01L29/66757H01L29/78618
    • Provided is a method of manufacturing a thin film transistor that can improve self-alignment. In this method, a semiconductor layer comprising a first doped region, a second doped region and a channel region is formed on a sacrificial layer on a first substrate. Next, the semiconductor layer is separated from the first substrate and is then coupled on a second substrate. Next, a dielectric layer is formed on the second substrate and the semiconductor layer, and a first photoresist layer is formed on the dielectric layer. Thereafter, the first photoresist layer is exposed to light from a rear surface of the second substrate by using the first doped region and the second doped region as a mask, to form a first mask pattern. Next, a gate electrode overlapping the channel region is formed on the dielectric layer by using the first mask pattern as a mask, and a source electrode and a drain electrode connected to the first doped region and the second doped region, respectively are formed to complete a thin film transistor.
    • 提供了一种可以改善自对准的薄膜晶体管的制造方法。 在该方法中,在第一衬底上的牺牲层上形成包括第一掺杂区域,第二掺杂区域和沟道区域的半导体层。 接下来,半导体层与第一衬底分离,然后耦合在第二衬底上。 接下来,在第二基板和半导体层上形成电介质层,在电介质层上形成第一光致抗蚀剂层。 此后,通过使用第一掺杂区域和第二掺杂区域作为掩模,将第一光致抗蚀剂层从第二基板的后表面曝光,以形成第一掩模图案。 接下来,通过使用第一掩模图案作为掩模在介电层上形成与沟道区重叠的栅电极,分别形成连接到第一掺杂区和第二掺杂区的源电极和漏极,以完成 薄膜晶体管。
    • 5. 发明授权
    • Method of manufacturing thin film transistor and thin film transistor substrate
    • 制造薄膜晶体管和薄膜晶体管基板的方法
    • US08119463B2
    • 2012-02-21
    • US12507725
    • 2009-07-22
    • Jae Bon KooIn-Kyu YouSeongdeok AhnKyoung Ik Cho
    • Jae Bon KooIn-Kyu YouSeongdeok AhnKyoung Ik Cho
    • H01L21/00H01L21/84
    • H01L29/78603H01L27/1266H01L29/66757H01L29/78618
    • Provided is a method of manufacturing a thin film transistor that can improve self-alignment. In this method, a semiconductor layer comprising a first doped region, a second doped region and a channel region is formed on a sacrificial layer on a first substrate. Next, the semiconductor layer is separated from the first substrate and is then coupled on a second substrate. Next, a dielectric layer is formed on the second substrate and the semiconductor layer, and a first photoresist layer is formed on the dielectric layer. Thereafter, the first photoresist layer is exposed to light from a rear surface of the second substrate by using the first doped region and the second doped region as a mask, to form a first mask pattern. Next, a gate electrode overlapping the channel region is formed on the dielectric layer by using the first mask pattern as a mask, and a source electrode and a drain electrode connected to the first doped region and the second doped region, respectively are formed to complete a thin film transistor.
    • 提供了一种可以改善自对准的薄膜晶体管的制造方法。 在该方法中,在第一衬底上的牺牲层上形成包括第一掺杂区域,第二掺杂区域和沟道区域的半导体层。 接下来,半导体层与第一衬底分离,然后耦合在第二衬底上。 接下来,在第二基板和半导体层上形成电介质层,在电介质层上形成第一光致抗蚀剂层。 此后,通过使用第一掺杂区域和第二掺杂区域作为掩模,将第一光致抗蚀剂层从第二基板的后表面曝光,以形成第一掩模图案。 接下来,通过使用第一掩模图案作为掩模在介电层上形成与沟道区重叠的栅电极,分别形成连接到第一掺杂区和第二掺杂区的源电极和漏极,以完成 薄膜晶体管。
    • 10. 发明授权
    • Method of manufacturing thin film transistor and thin film transistor substrate
    • 制造薄膜晶体管和薄膜晶体管基板的方法
    • US08378421B2
    • 2013-02-19
    • US13350037
    • 2012-01-13
    • Jae Bon KooIn-Kyu YouSeongdeok AhnKyoung Ik Cho
    • Jae Bon KooIn-Kyu YouSeongdeok AhnKyoung Ik Cho
    • H01L27/12
    • H01L29/78603H01L27/1266H01L29/66757H01L29/78618
    • A thin film transistor substrate. The thin film transistor substrate includes a substrate, an adhesive layer on the substrate, and a semiconductor layer having a first doped region, a second doped region and a channel region on the adhesive layer. The thin film transistor substrate further includes a first dielectric layer on the semiconductor layer, a gate electrode overlapping the channel region, a second dielectric layer on the first dielectric layer and the gate electrode, a source electrode disposed on the second insulating layer, and a drain electrode spaced apart from the source electrode on the source electrode. The channel region is disposed between the first doped region and the second doped region, and has a transmittance higher than those of the first doped region and the second doped region.
    • 薄膜晶体管基板。 薄膜晶体管衬底包括衬底,衬底上的粘合剂层,以及在粘合剂层上具有第一掺杂区域,第二掺杂区域和沟道区域的半导体层。 薄膜晶体管基板还包括半导体层上的第一介电层,与沟道区重叠的栅极电极,第一介电层上的第二电介质层和栅极电极,设置在第二绝缘层上的源电极和 漏电极与源电极上的源电极间隔开。 沟道区域设置在第一掺杂区域和第二掺杂区域之间,并且具有高于第一掺杂区域和第二掺杂区域的透射率的透射率。