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1. 发明授权

US08390364B2 Internal voltage generation circuit for semiconductor apparatus 失效
标题翻译：半导体装置的内部电压产生电路
公开(公告)号：US08390364B2
公开(公告)日：2013-03-05
申请号：US12843995
申请日：2010-07-27
申请人： Ki Han Kim , Hyun Woo Lee , Won Joo Yun
发明人： Ki Han Kim , Hyun Woo Lee , Won Joo Yun
IPC分类号： G05F1/10
CPC分类号： G11C5/147
摘要： A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison.
摘要翻译：用于产生内部电压的半导体装置包括控制代码输出块和内部电压产生块。控制代码输出块被配置为输出具有与内部电压的电压电平对应的代码值的可变代码。内部电压生成块被配置为将可变代码与设置代码进行比较，并且根据比较来控制内部电压的电压电平。

2. 发明授权

US08138812B2 Device for generating clock in semiconductor integrated circuit 有权
标题翻译：用于在半导体集成电路中产生时钟的装置
公开(公告)号：US08138812B2
公开(公告)日：2012-03-20
申请号：US12646608
申请日：2009-12-23
申请人： Won Joo Yun , Hyun Woo Lee , Ki Han Kim
发明人： Won Joo Yun , Hyun Woo Lee , Ki Han Kim
IPC分类号： G06F1/04
CPC分类号： G06F1/06 , H03L7/0812 , H03L7/0995 , H03L7/16
摘要： Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.
摘要翻译：半导体集成电路的各种实施例。根据一个示例性实施例，半导体集成电路包括被配置为产生多相内部时钟的多相时钟发生器; 第一边缘组合单元，被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第一频率的第一输出时钟，并将所述第一输出时钟发送到第一端口; 以及第二边缘组合单元，其被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第二频率的第二输出时钟，并将所述输出时钟发送到第二端口。

3. 发明授权

US07928783B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07928783B2
公开(公告)日：2011-04-19
申请号：US12493804
申请日：2009-06-29
申请人： Won Joo Yun , Hyun Woo Lee , Ki Han Kim
发明人： Won Joo Yun , Hyun Woo Lee , Ki Han Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/04 , H03K5/1565
摘要： A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.
摘要翻译：半导体集成电路包括：频率确定单元，被配置为确定半导体集成电路的操作速度并产生频率区域信号; 占空比控制单元，被配置为检测DLL时钟的占空比并产生占空比控制信号; 占空比校正单元，被配置为通过响应于频域信号校正输入时钟的占空比并响应于占空比控制信号来产生校正时钟; 以及被配置为通过控制校正时钟的相位来产生DLL时钟的DLL（延迟锁定环路）。

4. 发明申请

US20110025384A1 DEVICE FOR GENERATING CLOCK IN SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：用于在半导体集成电路中产生时钟的器件
公开(公告)号：US20110025384A1
公开(公告)日：2011-02-03
申请号：US12646608
申请日：2009-12-23
申请人： Won Joo YUN , Hyun Woo Lee , Ki Han Kim
发明人： Won Joo YUN , Hyun Woo Lee , Ki Han Kim
IPC分类号： H03L7/06 , G06F1/04
CPC分类号： G06F1/06 , H03L7/0812 , H03L7/0995 , H03L7/16
摘要： Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.
摘要翻译：半导体集成电路的各种实施例。根据一个示例性实施例，半导体集成电路包括被配置为产生多相内部时钟的多相时钟发生器; 第一边缘组合单元，被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第一频率的第一输出时钟，并将所述第一输出时钟发送到第一端口; 以及第二边缘组合单元，其被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第二频率的第二输出时钟，并将所述输出时钟发送到第二端口。

5. 发明授权

US08836370B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US08836370B2
公开(公告)日：2014-09-16
申请号：US13611298
申请日：2012-09-12
申请人： Ki Han Kim , Hyun Woo Lee , Dae Han Kwon , Chul Woo Kim , Soo Bin Lim
发明人： Ki Han Kim , Hyun Woo Lee , Dae Han Kwon , Chul Woo Kim , Soo Bin Lim
IPC分类号： H03K19/0175
CPC分类号： H03K19/094 , H03K19/0013 , H03K19/09482
摘要： A semiconductor apparatus includes a power supply changing unit. The power supply changing unit is configured to receive an enable signal and power supply voltage, generate first voltage or second voltage according to the enable signal, change a voltage level of the second voltage according to a level signal, and supply the first voltage or the second voltage as a driving voltage of an internal circuit, wherein the internal circuit receives a first input signal to output a second input signal.
摘要翻译：一种半导体装置，包括电源改变单元。电源改变单元被配置为接收使能信号和电源电压，根据使能信号产生第一电压或第二电压，根据电平信号改变第二电压的电压电平，并且提供第一电压或第二电压作为内部电路的驱动电压，其中内部电路接收第一输入信号以输出第二输入信号。

6. 发明授权

US08487679B2 Data output control circuit 有权
标题翻译：数据输出控制电路
公开(公告)号：US08487679B2
公开(公告)日：2013-07-16
申请号：US13028253
申请日：2011-02-16
申请人： Ki Han Kim , Hyun Woo Lee
发明人： Ki Han Kim , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/1057 , G11C7/1066 , G11C7/222 , H03L7/0818
摘要： A data output control circuit includes a DLL circuit and a delay detection unit. The DLL circuit is configured to generate a second internal clock by delaying a first internal clock generated from an external clock, compare a phase of the first internal clock with a phase of the second internal clock, and generate a DLL clock. The delay detection unit is configured to generate a sense signal whose logic level is changed according to a comparison result of a set time interval and a delay time interval during which the first internal clock is delayed in order to generate the second internal clock.
摘要翻译：数据输出控制电路包括DLL电路和延迟检测单元。 DLL电路被配置为通过延迟从外部时钟产生的第一内部时钟来产生第二内部时钟，将第一内部时钟的相位与第二内部时钟的相位进行比较，并生成DLL时钟。所述延迟检测单元被配置为根据设定的时间间隔的比较结果和延迟所述第一内部时钟的延迟时间间隔来生成其逻辑电平变化的感测信号，以便产生所述第二内部时钟。

7. 发明授权

US08519760B2 Device characteristic compensation circuit and semiconductor apparatus using the same 有权
标题翻译：器件特性补偿电路及使用其的半导体器件
公开(公告)号：US08519760B2
公开(公告)日：2013-08-27
申请号：US13219611
申请日：2011-08-27
申请人： Ki Han Kim , Hyun Woo Lee
发明人： Ki Han Kim , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/26 , H03L7/0816
摘要： A device characteristic compensation circuit includes a device characteristic detection block configured to detect one or more of a frequency of a clock signal and characteristics of devices, and generate a control code signal according to a detection result; and an internal voltage regulation unit configured to regulate a level of an internal voltage in response to the control code signal and generate a corrected internal voltage.
摘要翻译：一种器件特性补偿电路，包括：器件特性检测块，被配置为检测时钟信号的频率和器件的特性中的一个或多个，并根据检测结果生成控制码信号; 以及内部电压调节单元，其被配置为响应于所述控制代码信号来调节内部电压的电平并产生校正的内部电压。

8. 发明授权

US08411514B2 Multi-chip package including output enable signal generation circuit and data output control method thereof 有权
标题翻译：多芯片封装，包括输出使能信号发生电路及其数据输出控制方法
公开(公告)号：US08411514B2
公开(公告)日：2013-04-02
申请号：US12981453
申请日：2010-12-29
申请人： Ki Han Kim , Hyun Woo Lee
发明人： Ki Han Kim , Hyun Woo Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1066 , G11C7/222
摘要： An output enable signal generation circuit includes a latency decoder, a latch unit, a latency multiplexer, and an enable setting unit. The latency decoder is configured to decode a mode register set code and generate first and second CAS latency information. The latch unit is configured to output the latched first and second latency information as first and second latency signals. The latency multiplexer is configured to output the first or second latency signal as an output CAS latency signal in response to a chip select signal. The enable setting unit is configured to set an enable timing of an output enable signal.
摘要翻译：输出使能信号生成电路包括等待解码器，锁存单元，延迟复用器和使能设置单元。延迟解码器被配置为解码模式寄存器集代码并生成第一和第二CAS等待时间信息。锁存单元被配置为输出锁存的第一和第二等待时间信息作为第一和第二等待时间信号。延迟复用器被配置为响应于芯片选择信号而输出第一或第二等待时间信号作为输出CAS等待时间信号。使能设置单元被配置为设置输出使能信号的使能定时。

9. 发明申请

US20120194233A1 DEVICE CHARACTERISTIC COMPENSATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME 有权
标题翻译：装置特征补偿电路及其半导体装置
公开(公告)号：US20120194233A1
公开(公告)日：2012-08-02
申请号：US13219611
申请日：2011-08-27
申请人： Ki Han Kim , Hyun Woo Lee
发明人： Ki Han Kim , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/26 , H03L7/0816
摘要： A device characteristic compensation circuit includes a device characteristic detection block configured to detect one or more of a frequency of a clock signal and characteristics of devices, and generate a control code signal according to a detection result; and an internal voltage regulation unit configured to regulate a level of an internal voltage in response to the control code signal and generate a corrected internal voltage.
摘要翻译：一种器件特性补偿电路，包括：器件特性检测块，被配置为检测时钟信号的频率和器件的特性中的一个或多个，并根据检测结果生成控制码信号; 以及内部电压调节单元，其被配置为响应于所述控制代码信号来调节内部电压的电平并产生校正的内部电压。

10. 发明授权

US08373471B2 Semiconductor apparatus and DLL circuit using the same 有权
标题翻译：半导体装置和DLL电路使用相同
公开(公告)号：US08373471B2
公开(公告)日：2013-02-12
申请号：US12983187
申请日：2010-12-31
申请人： Ki Han Kim , Hyun Woo Lee
发明人： Ki Han Kim , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0816
摘要： A semiconductor apparatus includes: an update pulse generating unit configured to generate an update pulse every first period based on a frequency of a clock, and a control unit configured to control an output signal in response to an input signal and the update pulse, so that the output signal is varied based on the input signal.
摘要翻译：一种半导体装置，包括：更新脉冲发生单元，被配置为基于时钟的频率在每第一周期产生更新脉冲;以及控制单元，被配置为响应于输入信号和更新脉冲来控制输出信号，使得输出信号根据输入信号而变化。

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