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1. 发明申请

US20080288835A1 Test method, integrated circuit and test system 失效
标题翻译：测试方法，集成电路和测试系统
公开(公告)号：US20080288835A1
公开(公告)日：2008-11-20
申请号：US12050706
申请日：2008-03-18
申请人： Wolfgang Ruf , Martin Schnell
发明人： Wolfgang Ruf , Martin Schnell
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/06 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/20 , G11C29/40 , G11C2029/3602
摘要： The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock.
摘要翻译：本文公开的测试方法，集成电路和测试系统实施例涉及测试至少一个集成电路，其使用内部操作时钟并具有第一数量的地址引脚，第二数量的命令引脚和至少接收到的地址产生电路一个编码的地址信息项，其使用小于第一个数字的第三个地址引脚数，并将另一个地址引脚提供为第四个空闲地址引脚，其中使用命令引脚传送至少一个第一命令，使用具有比内部操作时钟更低的速率的测试时钟，使用第四数量的地址引脚的至少一部分从测试装置传输到集成电路的至少一个第二命令。

2. 发明申请

US20080247252A1 Semiconductor Memory Device with Temperature Control 有权
标题翻译：具有温度控制的半导体存储器件
公开(公告)号：US20080247252A1
公开(公告)日：2008-10-09
申请号：US11696777
申请日：2007-04-05
申请人： Wolfgang Ruf , Martin Schnell , Rainer Kommling
发明人： Wolfgang Ruf , Martin Schnell , Rainer Kommling
IPC分类号： G11C7/00 , G11C5/14 , G11C8/00
CPC分类号： G11C7/04 , G11C5/14 , G11C5/143
摘要： A memory device in a semiconductor substrate includes at least one temperature sensor to provide a temperature dependent signal and at least one circuit to dissipate heat in response to a control signal. A control circuit is coupled to the at least one circuit and is operable to generate the control signal in response to the temperature dependent signal.
摘要翻译：半导体衬底中的存储器件包括至少一个温度传感器以提供与温度相关的信号，以及响应于控制信号而散热的至少一个电路。控制电路耦合到所述至少一个电路，并且可操作以响应于与温度相关的信号而产生控制信号。

3. 发明申请

US20050270891A1 Backwards-compatible memory module 有权
公开(公告)号：US20050270891A1
公开(公告)日：2005-12-08
申请号：US11127536
申请日：2005-05-12
申请人： Bjorn Flach , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
发明人： Bjorn Flach , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
IPC分类号： G11C5/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C11/4093 , G11C11/4096
CPC分类号： G11C7/1078 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/4096 , G11C2207/107
摘要： Memory module (1, 101, 201) having: at least one memory cell array (6, 106, 206), with the memory cells each being addressable by at least one address and being organized in organization units comprising a predetermined number of memory cells which can be driven jointly and at the same time; a clocked read/write control device (11, 111, 211), which is clocked with a first clock signal (CLK1) and which is coupled to the memory cell array (6, 106, 206), for writing data to and reading data from the memory cells as a function of address signals (ADR); a prefetch register unit (13, 113, 213), which is coupled to the read/write control device (11, 111, 211), for initial storage of data which is read from the memory cell array (6, 106, 206) and having two or more prefetch registers (14-17, 114-117, 214-217), whose respective register size corresponds to the predetermined number of memory cells in the organization units; a controlled switching device (23, 123, 223), which is coupled to the prefetch register unit (13, 113, 213), for outputting the data (DQs) which is initially stored in the prefetch registers (14-17, 114-117, 214-217) at data inputs/outputs (5, 105, 205) of the memory module (1, 101, 201), with the switching device (23, 123, 223) successively coupling the prefetch registers (14-17, 114-117, 214-217) to the data inputs/outputs (5, 105, 205) of the memory module (1, 101, 201) in a first operating mode of the memory module (1, 101, 201), controlled by a second clock signal (CLK2), with the number of data inputs/outputs (5, 105, 205) corresponding to the number of memory cells in the organization units, and coupling at least one of the prefetch registers (14-17, 114-117, 214-217) to the data inputs/outputs (5, 105, 205) of the memory module (1, 101, 201) in a second operating mode controlled by at least one of the address signals (ADR).

4. 发明申请

US20050055618A1 Test arrangement and method for selecting a test mode output channel 审中-公开
标题翻译：选择测试模式输出通道的测试方法和方法
公开(公告)号：US20050055618A1
公开(公告)日：2005-03-10
申请号：US10926371
申请日：2004-08-25
申请人： Thomas Finteis , Bjorn Flach , Klaus Hoffman , Andreas Logisch , Wolfgang Ruf , Martin Schnell
发明人： Thomas Finteis , Bjorn Flach , Klaus Hoffman , Andreas Logisch , Wolfgang Ruf , Martin Schnell
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3187 , G01R31/319 , G06F11/00 , G06F11/273
CPC分类号： G06F11/273
摘要： The invention provides a test arrangement for testing circuit units under test (101, 101a-101n) having a test apparatus for holding the circuit units under test (101, 101a-101n), input/output channels (DQ0-DQn) for connecting the circuit units under test (101, 101a-101n) to the test apparatus and for data interchange, and test mode output channels (103, 103a-103n) for outputting a test result signal (104, 104a-104n), where at least one diversion unit (102, 102a-102n) for connecting one of the test mode output channels (103, 103a-103n) to one of the input/output channels (DQ0-DQn) is provided in the circuit units under test (101, 101a-101n) so that the test result signal (104, 104a-104n) which is output from the circuit unit under test (101, 101a-101n) can be diverted from the circuit unit under test (101, 101a-101n) to a prescribable one of the input/output channels (DQ0-DQn).
摘要翻译：本发明提供一种用于测试被测电路单元（101,101a-101n）的测试装置，该测试装置具有用于保持被测电路单元（101,101a-101n）的测试装置，用于连接所述电路单元的输入/输出通道（DQ0-DQn）被测试电路单元（101,101a-101n）和用于数据交换的测试模式输出通道（103,103a-103n），用于输出测试结果信号（104,104a-104n），其中至少一个用于将测试模式输出通道（103,103a-103n）中的一个连接到输入/输出通道（DQ0-DQn）之一的转向单元（102,102〜102n）设置在被测电路单元（101,101a -101n），使得从被测电路单元（101,101a-101n）输出的测试结果信号（104,104a-104n）可以从被测电路单元（101,101a-101n）转移到可输入/输出通道之一（DQ0-DQn）。

5. 发明授权

US07760569B2 Semiconductor memory device with temperature control 有权
标题翻译：具有温度控制的半导体存储器件
公开(公告)号：US07760569B2
公开(公告)日：2010-07-20
申请号：US11696777
申请日：2007-04-05
申请人： Wolfgang Ruf , Martin Schnell , Rainer Kömmling
发明人： Wolfgang Ruf , Martin Schnell , Rainer Kömmling
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C5/14 , G11C5/143
摘要： A memory device in a semiconductor substrate includes at least one temperature sensor to provide a temperature dependent signal and at least one circuit to dissipate heat in response to a control signal. A control circuit is coupled to the at least one circuit and is operable to generate the control signal in response to the temperature dependent signal.
摘要翻译：半导体衬底中的存储器件包括至少一个温度传感器以提供与温度相关的信号，以及响应于控制信号而散热的至少一个电路。控制电路耦合到所述至少一个电路，并且可操作以响应于与温度相关的信号而产生控制信号。

6. 发明授权

US07757145B2 Test method, integrated circuit and test system 失效
标题翻译：测试方法，集成电路和测试系统
公开(公告)号：US07757145B2
公开(公告)日：2010-07-13
申请号：US12050706
申请日：2008-03-18
申请人： Wolfgang Ruf , Martin Schnell
发明人： Wolfgang Ruf , Martin Schnell
IPC分类号： G11C29/00 , G01R31/28 , G01R31/02 , G01R31/26
CPC分类号： G11C29/06 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/20 , G11C29/40 , G11C2029/3602
摘要： The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock.
摘要翻译：本文公开的测试方法，集成电路和测试系统实施例涉及测试至少一个集成电路，其使用内部操作时钟并具有第一数量的地址引脚，第二数量的命令引脚和至少接收到的地址产生电路一个编码的地址信息项，其使用小于第一个数字的第三个地址引脚数，并将另一个地址引脚提供为第四个空闲地址引脚，其中使用命令引脚传送至少一个第一命令，使用具有比内部操作时钟更低的速率的测试时钟，使用第四数量的地址引脚的至少一部分从测试装置传输到集成电路的至少一个第二命令。

7. 发明授权

US07414421B2 Insertable calibration device 失效
标题翻译：可插入校准装置
公开(公告)号：US07414421B2
公开(公告)日：2008-08-19
申请号：US11290138
申请日：2005-11-30
申请人： Björn Flach , Andreas Logisch , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
发明人： Björn Flach , Andreas Logisch , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
IPC分类号： G01R31/02
CPC分类号： G01R35/005 , G11C29/56 , G11C2029/5602
摘要： An insertable calibration device for a programmable tester apparatus comprises at least one calibration unit and a control unit. The progammable tester apparatus is configured to test at least one electronic device with electronic circuits. The progammable tester apparatus comprises a holding device, contact-making devices for the electronic device, and tester channels for coupling in signals to the electronic device. The calibration unit is connected to a first tester channel to be calibrated. The calibration unit is configured to detect a calibration signal edge of a calibration signal that is transmitted by the tester apparatus at a certain transmission instant, to detect a reference signal edge of a reference signal that is transmitted by the tester apparatus via a second tester channel at a reference instant, to compare the instants at which the two signal edges arrive, and to output a comparison result. The control unit evaluates the comparison results and can be used to program the transmission instants in such a way that the instants at which the calibration signal edge and the reference signal edge arrive, for the compensation of signal propagation time differences, are substantially identical. The calibration device has the same form and connections as the electric device and is insertable into the holding device with an accurate fit instead of the electronic device.
摘要翻译：用于可编程测试仪器的可插入校准装置包括至少一个校准单元和控制单元。可程序测试仪装置被配置为使用电子电路测试至少一个电子设备。可程序测试仪器包括保持装置，用于电子装置的接触装置和用于将信号耦合到电子装置的测试仪通道。校准单元连接到要校准的第一测试仪通道。校准单元被配置为检测在某一传输时刻由测试仪器发送的校准信号的校准信号边沿，以检测由测试仪器通过第二测试器通道发送的参考信号的参考信号边沿在参考时刻，比较两个信号边缘到达的时刻，并输出比较结果。控制单元评估比较结果，并且可以用于对传输时刻进行编程，使得校准信号边沿和参考信号边缘到达的时刻用于信号传播时间差的补偿基本相同。校准装置具有与电气装置相同的形式和连接，并且可以精确配合而不是电子装置插入到保持装置中。

8. 发明申请

US20060156149A1 Semiconductor component, arrangement and method for characterizing a tester for semiconductor components 失效
标题翻译：用于表征半导体部件的测试器的半导体部件，布置和方法
公开(公告)号：US20060156149A1
公开(公告)日：2006-07-13
申请号：US11257401
申请日：2005-10-25
申请人： Andreas Logisch , Monica Martins , Bjorn Flach , Wolfgang Ruf , Martin Schnell , Ana Leao
发明人： Andreas Logisch , Monica Martins , Bjorn Flach , Wolfgang Ruf , Martin Schnell , Ana Leao
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/028 , G11C29/56
摘要： A tester for semiconductor components with a plurality of channels is connected to a specific semiconductor component in order to characterize the signal path between tester and semiconductor component under production conditions. The specific semiconductor component includes measuring units that are connected to connection contacts and in each case provide the functionality of a signal generator, a signal detector, a digital communication interface and a receiving unit for trigger signals. The specific semiconductor component further includes a trigger logic to convey trigger signals between the receiving unit of a first one and the signal generator or detector of a second one of the measuring units.
摘要翻译：具有多个通道的半导体部件的测试器连接到特定的半导体部件，以便在生产条件下表征测试仪和半导体部件之间的信号路径。特定的半导体部件包括连接到连接触点的测量单元，并且在每种情况下提供信号发生器，信号检测器，数字通信接口和用于触发信号的接收单元的功能。特定半导体部件还包括用于在第一个的接收单元和第二个测量单元的信号发生器或检测器之间传送触发信号的触发逻辑。

9. 发明申请

US20060149491A1 Insertable calibration device 失效
标题翻译：可插入校准装置
公开(公告)号：US20060149491A1
公开(公告)日：2006-07-06
申请号：US11290138
申请日：2005-11-30
申请人： Bjorn Flach , Andreas Logisch , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
发明人： Bjorn Flach , Andreas Logisch , Monica De Castro Martins , Wolfgang Ruf , Martin Schnell
IPC分类号： G06F19/00
CPC分类号： G01R35/005 , G11C29/56 , G11C2029/5602
摘要： An insertable calibration device for a programmable tester apparatus comprises at least one calibration unit and a control unit. The progammable tester apparatus is configured to test at least one electronic device with electronic circuits. The progammable tester apparatus comprises a holding device, contact-making devices for the electronic device, and tester channels for coupling in signals to the electronic device. The calibration unit is connected to a first tester channel to be calibrated. The calibration unit is configured to detect a calibration signal edge of a calibration signal that is transmitted by the tester apparatus at a certain transmission instant, to detect a reference signal edge of a reference signal that is transmitted by the tester apparatus via a second tester channel at a reference instant, to compare the instants at which the two signal edges arrive, and to output a comparison result. The control unit evaluates the comparison results and can be used to program the transmission instants in such a way that the instants at which the calibration signal edge and the reference signal edge arrive, for the compensation of signal propagation time differences, are substantially identical. The calibration device has the same form and connections as the electric device and is insertable into the holding device with an accurate fit instead of the electronic device.
摘要翻译：用于可编程测试仪器的可插入校准装置包括至少一个校准单元和控制单元。可程序测试仪装置被配置为使用电子电路测试至少一个电子设备。可程序测试仪器包括保持装置，用于电子装置的接触装置和用于将信号耦合到电子装置的测试仪通道。校准单元连接到要校准的第一测试仪通道。校准单元被配置为检测在某一传输时刻由测试仪器发送的校准信号的校准信号边沿，以检测由测试仪器通过第二测试器通道发送的参考信号的参考信号边沿在参考时刻，比较两个信号边缘到达的时刻，并输出比较结果。控制单元评估比较结果，并且可以用于对传输时刻进行编程，使得校准信号边沿和参考信号边缘到达的时刻用于信号传播时间差的补偿基本相同。校准装置具有与电气装置相同的形式和连接，并且可以精确配合而不是电子装置插入到保持装置中。

10. 发明申请

US20090051383A1 Test Method and Production Method for a Semiconductor Circuit Composed of Subcircuits 审中-公开
标题翻译：由子电路组成的半导体电路的测试方法和制作方法
公开(公告)号：US20090051383A1
公开(公告)日：2009-02-26
申请号：US11885383
申请日：2005-03-04
申请人： Wolfgang Ruf , Martin Schnell
发明人： Wolfgang Ruf , Martin Schnell
IPC分类号： G01R31/26 , G06F17/50
CPC分类号： G01R31/31917
摘要： Test method and production method for testing a semiconductor circuit comprising a plurality of subcircuits. The semiconductor circuit is produced according to specification stipulations comprising a design based on a hardware description language for a functional implementation, a logic synthesis for a structural implementation, a layout design for a topological implementation and processing a semiconductor substrates in accordance with the layout design. A test pattern having test signal sequences is coupled into the semiconductor circuit and functional results are coupled out. Test signal lengths and/or test signal levels are selected from a previously generated test parameter list, wherein the test parameter list is generated during the logic synthesis.
摘要翻译：用于测试包括多个子电路的半导体电路的测试方法和制造方法。半导体电路根据包括基于用于功能实现的硬件描述语言的设计，用于结构实现的逻辑综合，用于拓扑实现的布局设计和根据布局设计来处理半导体衬底的设计来制造。具有测试信号序列的测试图案耦合到半导体电路中，并且结合功能结果。从先前生成的测试参数列表中选择测试信号长度和/或测试信号电平，其中在逻辑合成期间产生测试参数列表。

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