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    • 1. 发明授权
    • Pipeline processor
    • US4524455A
    • 1985-06-18
    • US269143
    • 1981-06-01
    • Wlodzimierz HolsztynskiStephen S. Wilson
    • Wlodzimierz HolsztynskiStephen S. Wilson
    • G06F15/80G06T1/20G06K9/36
    • G06T1/20G06F15/8015
    • A system particularly suited for serially processing spatially oriented data such as data matrices includes a plurality of serially connected processing cells for performing a number of successive, different operations on the data using pipeline processing techniques. In one embodiment, each unit cell comprises a memory in the form of a shift register for storing data received from the neighboring, upstream cell. The data is transferred from the memory to a time delaying storage medium such as a latch and to a processing circuit which operates on the data and provides data output to the neighboring, downstream cell. In another embodiment, a simple parallel-in, parallel-out latch is employed as the cell memory thereby allowing the processing circuit to simultaneously access all of the data stored in memory. Data is output from the latch in pre-determined groups and is multiplexed to one portion of the processing circuit. One of the data groups output from the latch is delayed by a shift register and then delivered to another portion of the processing circuit which selectively receives data from the first portion. A central controller connected to each cell controls the transfer of data within and between the cells.
    • 2. 发明授权
    • Pipeline processor
    • 管道处理器
    • US4574394A
    • 1986-03-04
    • US598724
    • 1984-04-10
    • Wlodzimierz HolsztynskiStephen S. Wilson
    • Wlodzimierz HolsztynskiStephen S. Wilson
    • G06F15/80G06T1/20G06K9/36
    • G06F15/8015G06T1/20
    • A system particularly suited for serially processing spatially oriented data such as data matrices includes a plurality of serially connected processing cells for performing a number of successive, different operations on the data using pipeline processing techniques. In one embodiment, each unit cell comprises a memory in the form of a shift register for storing data received from the neighboring, upstream cell. The data is transferred from the memory to a time delaying storage medium such as a latch and to a processing circuit which operates on the data and provides data output to the neighboring, downstream cell. In another embodiment, a simple parallel-in, parallel-out latch is employed as the cell memory thereby allowing the processing circuit to simultaneously access all of the data stored in memory. Data is output from the latch in pre-determined groups and is multiplexed to one portion of the processing circuit. One of the data groups output from the latch is delayed by a shift register and then delivered to another portion of the processing circuit which selectively receives data from the first portion. A central controller connected to each cell controls the transfer of data within and between the cells.
    • 特别适用于串行处理诸如数据矩阵的空间定向数据的系统包括多个串行连接的处理单元,用于使用流水线处理技术对数据执行多个连续不同的操作。 在一个实施例中,每个单元单元包括用于存储从相邻上游单元接收的数据的移位寄存器形式的存储器。 数据从存储器传送到诸如锁存器的时间延迟的存储介质和对数据进行操作的处理电路,并向相邻的下游单元提供数据输出。 在另一个实施例中,采用简单并行并行输出锁存器作为单元存储器,从而允许处理电路同时访问存储在存储器中的所有数据。 数据从预定组中的锁存器输出,并被复用到处理电路的一部分。 从锁存器输出的数据组中的一个被移位寄存器延迟,然后被递送到处理电路的从第一部分选择性地接收数据的另一部分。 连接到每个单元的中央控制器控制单元内和之间的数据传送。
    • 3. 发明授权
    • Cellular digital array processor
    • 蜂窝数字阵列处理器
    • US4215401A
    • 1980-07-29
    • US946588
    • 1978-09-28
    • Wlodzimierz HolsztynskiStephen S. Wilson
    • Wlodzimierz HolsztynskiStephen S. Wilson
    • G06F15/80G06F7/00
    • G06F15/8023
    • A rectangular digital logic array for performing transformations on data matrices for solving wave equations, image processing problems and the like, includes a plurality of identical cells each having a processing element which receives one of its inputs from a single bit accumulator and provides its output to a similar single bit accumulator. The input accumulators of each row in the array are formed by a single parallel input, parallel output shift register and the output accumulators of each column in the array are similarly formed by a parallel input, parallel output shift register. The shift registers operate to connect each cell except those at the edge of the array with two neighboring cells along one axis and two neighboring cells along the orthogonal axis. Four edge shift registers bordering the array allow data to be transferred into and out of the cells and a central processor connected to each of the cells controls the sequence of cell operations and the transfer of data between cells for all cells simultaneously. The simple cell and interconnection structure allows the economical formation of large arrays so that very high processing speeds may be achieved despite the multiple processing steps which each elemental cell must undergo in order to perform a complex computation.
    • 用于对用于求解波方程,图像处理问题等的数据矩阵执行变换的矩形数字逻辑阵列包括多个相同的单元,每个单元具有处理单元,该处理单元从单个位累加器接收其输入中的一个,并将其输出提供给 一个类似的单位累加器。 阵列中每行的输入累加器由单个并行输入,并行输出移位寄存器和阵列中每列的输出累加器由并行输入并行输出移位寄存器类似地形成。 移位寄存器用于连接除阵列边缘之外的每个单元,沿着一个轴和两个相邻的单元沿着正交轴与两个相邻的单元格连接。 与阵列相邻的四个边缘移位寄存器允许将数据传入和传出单元,连接到每个单元的中央处理器同时控制单元格操作的顺序和单元格之间的数据传输。 简单的单元和互连结构允许经济地形成大阵列,使得尽管多个处理步骤,每个元件单元必须经历以执行复杂的计算,但是可以实现非常高的处理速度。
    • 7. 发明申请
    • Spectral Selective Solar Control Film Containing an Air Layer for Windows
    • 含有空气层的光谱选择性太阳能控制膜
    • US20110013273A1
    • 2011-01-20
    • US12762486
    • 2010-04-19
    • Stephen S. WilsonBart WilsonSeth Wilson
    • Stephen S. WilsonBart WilsonSeth Wilson
    • G02B5/26B32B37/12
    • G02B5/26B32B7/06B32B17/10
    • A building structure having a high efficiency solar control system is provided. The building structure may have a window defined by a sheet of glass and a film mounted to its exterior side. There may be a gap between the film and the glass wherein the film, film and gap, or gap provides thermal insulation. The film may reflect solar radiation in the near and mid infrared ranges yet allow high transmission of light in the visible range such that the occupants of the building structure may view his/her surroundings through the window. The film may have a layer of silver which reflects the solar radiation in the near and mid infrared ranges. Since the silver is susceptible to oxidation and turns the silver into a black body which absorbs the near and mid infrared radiation, a protective layer on the exterior of the infrared reflecting layer may be designed to slow the rate of oxidation of the silver layer to an acceptable level. The silver layer may be sandwiched between the glass which does not allow oxygen to diffuse there through and reach the layer of silver and the protective layer having a certain thickness which slows down the rate of oxygen diffusion to an acceptable level.
    • 提供了具有高效太阳能控制系统的建筑结构。 建筑结构可以具有由玻璃板和安装到其外侧的膜限定的窗口。 膜和玻璃之间可能存在间隙,其中膜,膜和间隙或间隙提供热绝缘。 该影片可以在近红外范围和中红外范围内反射太阳辐射,但允许在可见光范围内的高透射率,使得建筑结构的乘客可以通过窗户观看他/她的周围环境。 该膜可以具有在近红外范围和中红外范围内反射太阳辐射的一层银。 由于银易于氧化并且将银变成吸收近红外辐射和中红外辐射的黑体,所以红外反射层外部的保护层可被设计成将银层的氧化速率降低到 可接受水平 银层可以夹在玻璃之间,玻璃不允许氧在其中扩散并到达银层,并且具有一定厚度的保护层将氧扩散速率降低到可接受的水平。
    • 8. 发明授权
    • Phased array antenna having reduced beam settling times and related methods
    • 具有减小的光束稳定时间的相控阵天线和相关方法
    • US06690324B2
    • 2004-02-10
    • US09991495
    • 2001-11-09
    • David Kenyon VailFrank J. TaborDaniel P. BlomStephen S. Wilson
    • David Kenyon VailFrank J. TaborDaniel P. BlomStephen S. Wilson
    • H01Q322
    • H01Q1/38H01Q3/26H01Q3/36
    • A phased array antenna may include a substrate and a plurality of phased array antenna elements carried by the substrate. The phased array antenna may also include a plurality of antenna element controllers for the phased array antenna elements and a central controller for providing beam steering commands and edge trigger synchronization signals for the antenna element controllers. Furthermore, each of the antenna element controllers may store a respective next beam steering command and implement the respective next beam steering command as a respective active beam steering command responsive to the edge trigger synchronization signal from the central controller. The edge trigger synchronization signal may be delivered substantially simultaneously to all of the antenna element controllers, and each antenna element controller may detect the edge trigger synchronization pulse only during a predetermined time window, for example.
    • 相控阵天线可以包括衬底和由衬底承载的多个相控阵天线元件。 相控阵天线还可以包括用于相控阵天线元件的多个天线元件控制器和用于为天线元件控制器提供波束控制命令和边沿触发同步信号的中央控制器。 此外,每个天线元件控制器可以存储相应的下一个波束转向命令,并且响应于来自中央控制器的边沿触发同步信号,实现相应的下一个波束控制指令作为相应的主动波束操纵指令。 边缘触发同步信号可以基本上同时发送到所有天线元件控制器,并且每个天线元件控制器可以仅在预定时间窗口期间检测边缘触发同步脉冲。