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1. 发明授权

US10418113B2 Operation method for suppressing floating gate (FG) coupling 有权
公开(公告)号：US10418113B2
公开(公告)日：2019-09-17
申请号：US16361258
申请日：2019-03-22
申请人： Winbond Electronics Corp.
发明人： Naoaki Sudo
IPC分类号： G11C16/26 , G11C7/10 , G11C16/10 , G11C16/34 , G11C16/04 , G11C7/02 , G11C7/18
摘要： A NAND flash memory suppresses an influence caused by FG coupling and has high reliability. The flash memory of the invention includes: a memory array formed with a plurality of NAND strings; a row selection unit selecting rows of the memory array; and a bit line selection circuit (200) selecting even-numbered pages or odd-numbered pages of the selected row. The even-numbered pages (BL0, BL1, BL4, BL5) include a plurality of pairs of adjacent bit line pairs, the odd-numbered pages (BL2, BL3, BL6, BL7) include a plurality of pairs of adjacent bit line pairs, and the bit lines of the even-numbered page and the bit lines of the odd-numbered page are arranged alternately.

2. 发明授权

US10304543B2 Semiconductor memory device for improving high temperature data retention 有权
公开(公告)号：US10304543B2
公开(公告)日：2019-05-28
申请号：US15666576
申请日：2017-08-02
申请人： Winbond Electronics Corp.
发明人： Makoto Senoo , Naoaki Sudo
IPC分类号： G11C16/04 , G11C16/16 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/34 , G11C7/04 , G11C16/10
摘要： A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element detennines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.

3. 发明授权

US09612753B2 Semiconductor memory apparatus and data processing method 有权
公开(公告)号：US09612753B2
公开(公告)日：2017-04-04
申请号：US14923452
申请日：2015-10-27
申请人： Winbond Electronics Corp.
发明人： Naoaki Sudo
IPC分类号： G06F3/06 , G11C16/10 , G11C7/10 , G11C16/04 , G11C16/26 , G11C16/34
CPC分类号： G06F3/061 , G06F3/0638 , G06F3/0679 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3427
摘要： A semiconductor memory apparatus is provided. The semiconductor memory apparatus does not require additional identification information to perform data scrambling and improves the reliability, where the identification information is used to identify whether it is an erased data or a programmed data. A flash memory of the present disclosure includes a scrambling unit 120 scrambling data between an input/output buffer 110 and a page buffer 160. The scrambling unit 120 includes a writing encoder 200 and a reading decoder 220. When an input data is equal to a predetermined bit string, the writing encoder 200 skips the scrambling of the input data. When a read data of the page buffer 160 is equal to the predetermined bit string, the reading decoder 220 skips the descrambling of the read data.

4. 发明申请

US20160283113A1 SEMICONDUCTOR MEMORY APPARATUS AND DATA PROCESSING METHOD 有权
标题翻译：半导体存储器和数据处理方法
公开(公告)号：US20160283113A1
公开(公告)日：2016-09-29
申请号：US14923452
申请日：2015-10-27
申请人： Winbond Electronics Corp.
发明人： Naoaki Sudo
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0638 , G06F3/0679 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3427
摘要： A semiconductor memory apparatus is provided. The semiconductor memory apparatus does not require additional identification information to perform data scrambling and improves the reliability, where the identification information is used to identify whether it is an erased data or a programmed data. A flash memory of the present disclosure includes a scrambling unit 120 scrambling data between an input/output buffer 110 and a page buffer 160. The scrambling unit 120 includes a writing encoder 200 and a reading decoder 220. When an input data is equal to a predetermined bit string, the writing encoder 200 skips the scrambling of the input data. When a read data of the page buffer 160 is equal to the predetermined bit string, the reading decoder 220 skips the descrambling of the read data.
摘要翻译：提供半导体存储装置。半导体存储装置不需要额外的识别信息来执行数据加扰并提高可靠性，其中使用识别信息来识别是否是擦除数据或编程数据。本公开的闪速存储器包括加扰单元120对输入/输出缓冲器110和页缓冲器160之间的数据进行加扰。加扰单元120包括写入编码器200和读取解码器220.当输入数据等于写入编码器200跳过输入数据的加扰。当页面缓冲器160的读取数据等于预定位串时，读取解码器220跳过读取数据的解扰。

5. 发明授权

US11417403B2 Semiconductor device 有权
公开(公告)号：US11417403B2
公开(公告)日：2022-08-16
申请号：US17148591
申请日：2021-01-14
申请人： Winbond Electronics Corp.
发明人： Naoaki Sudo
IPC分类号： G11C16/30
摘要： A semiconductor device capable of automatically transitioning from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes: internal circuits capable of operating in response to an input signal from an input/output circuit; and a controller capable of controlling operations of the internal circuits. The internal circuit supporting the DPD mode includes: a measurement part, measuring a time since a time point of the semiconductor device entering the standby mode; a transition time detection part, detecting a case where a measurement time of the measurement part has reached a certain time; and a DPD signal generation part, generating a power down enable signal for further reducing power consumption in the standby mode when a transition time is detected.

6. 发明申请

US20220246217A1 SEMICONDUCTOR APPARATUS AND CONTINUOUS READOUT METHOD 有权
公开(公告)号：US20220246217A1
公开(公告)日：2022-08-04
申请号：US17512687
申请日：2021-10-28
申请人： Winbond Electronics Corp.
发明人： Naoaki Sudo , Makoto Senoo
IPC分类号： G11C16/26 , G11C16/04 , G06F11/10
摘要： A semiconductor apparatus and a continuous readout method for improving prior continuous readout are provided. A flash memory includes: a NAND memory cell array, an input/output circuit, an ECC circuit, a controller, a word-line selection circuit, a page buffer/readout circuit, and a row selection circuit. When performing the continuous readout of pages, the controller performs an array readout of a first half page of a selection page on the memory cell array and an array readout of a second half page of the selection page on the memory cell array independently, and continuously outputs the respectively read data of the half pages in synchronization with a clock signal.

7. 发明申请

US20190221268A1 SEMICONDUCTOR MEMORY DEVICE FOR IMPROVING HIGH TEMPERATURE DATA RETENTION 审中-公开
公开(公告)号：US20190221268A1
公开(公告)日：2019-07-18
申请号：US16361242
申请日：2019-03-22
申请人： Winbond Electronics Corp.
发明人： Makoto Senoo , Naoaki Sudo
IPC分类号： G11C16/16 , G11C16/34 , G11C16/10 , G11C7/04 , G11C16/08 , G11C16/04 , G11C16/26 , G11C16/24
CPC分类号： G11C16/16 , G11C7/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3459
摘要： A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element determines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.

8. 发明申请

US20190214095A1 SEMICONDUCTOR STORAGE DEVICE AND OPERATION METHOD THEREOF 审中-公开
公开(公告)号：US20190214095A1
公开(公告)日：2019-07-11
申请号：US16242017
申请日：2019-01-08
申请人： Winbond Electronics Corp.
发明人： Naoaki Sudo
IPC分类号： G11C16/26 , G11C29/04 , G01R19/165 , G11C16/30
摘要： A semiconductor memory device and an operation method thereof that can accurately read setting information from a memory cell array when a power supply is turned on are provided. The flash memory includes a memory cell array, a detecting portion, a ROM and a control portion. The detecting portion detects that the power supply is turned on. The ROM stores at least a code for performing a reading operation of the memory cell array and stores a special code in a specific address. The control portion controls the reading of the ROM. When the detecting portion detects the power-on of the power supply, the control portion reads the special code from the ROM and determines whether the read special code is correct or not, reads the code if the determination is correct and again reads the special code if the determination is incorrect.

9. 发明授权

US10025707B2 Non-volatile semiconductor memory device 有权
公开(公告)号：US10025707B2
公开(公告)日：2018-07-17
申请号：US15703997
申请日：2017-09-14
申请人： Winbond Electronics Corp.
发明人： Naoaki Sudo
IPC分类号： G11C7/10 , G06F12/02 , G06F3/06 , G06F11/10 , G06F12/126 , G11C16/34 , G11C29/42 , G11C29/44 , G11C16/04 , G11C29/04
摘要： A flash memory includes a memory array including a memory mat MAT-0, MAT-1; a page buffer 170-0, holding data read from the memory mat MAT-0; a page buffer 170-1, holding data read from the memory mat MAT-1; an ECC circuit 140, performing data error checking and correction; an output buffer 110 for outputting data; and a transferring control element, controlling transferring of data between the page buffer 170-0, page buffer 170-1, ECC circuit 140 and output buffer 110. When the memory mat MAT-0 is selected, the transferring control element transfers data held by the page buffer 170-0 to the page buffer 170-1 of the memory mat MAT-1.

10. 发明申请

US20170221567A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20170221567A1
公开(公告)日：2017-08-03
申请号：US15182593
申请日：2016-06-15
申请人： Winbond Electronics Corp.
发明人： Kazuki Yamauchi , Naoaki Sudo
IPC分类号： G11C16/10 , G11C29/52 , G06F11/10 , G11C16/34 , G11C16/30
CPC分类号： G11C16/10 , G06F11/1068 , G11C16/30 , G11C16/3459 , G11C29/52 , G11C2211/5621
摘要： A non-volatile semiconductor memory device is provided. A determination circuit 200 used to determine the suspected qualification is connected with a plurality of page buffer/sensing circuits 170 via wirings PB_UP, PB_MG, PB_DIS. The page buffer/sensing circuit 170 includes a transistor Q2 in which a reference current Iref flows through a transistor Q1 when the programming verification is unqualified. The determination circuit 200 includes a comparator CMP, a voltage of the wiring PB_UP is supplied to one of input terminals of the comparator CMP, and a reference voltage Vref is supplied to another one of the input terminals. The reference voltage Vref is generated by a reference current (Iref*N) whose amount is corresponding to an unqualified bit number (N) which is determined to be suspectedly qualified.

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