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1. 发明授权

US06263397B1 Mechanism for delivering interrupt messages 有权
标题翻译：传递中断消息的机制
公开(公告)号：US06263397B1
公开(公告)日：2001-07-17
申请号：US09206995
申请日：1998-12-07
申请人： William S. Wu , Mani Azimi , Stephen Pawlowski , Daniel G. Lau , M. Jayakumar
发明人： William S. Wu , Mani Azimi , Stephen Pawlowski , Daniel G. Lau , M. Jayakumar
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.
摘要翻译： I / O代理通过芯片组将中断消息传递到连接到多个处理器的系统总线。中断消息包括事务类型和目标标识。系统总线上的服务处理器将目的地标识与其自己的标识相匹配，以确定它是否是中断消息的预期接收者。 I / O代理将与中断相关的数据写入芯片组内的缓冲队列。在发送中断消息之前，芯片组会自动将缓冲队列的内容刷新到主存储器。中断传送机制避免了芯片组和I / O代理之间的握手操作的复杂性和延迟。

2. 发明授权

US5848279A Mechanism for delivering interrupt messages 失效
标题翻译：传递中断消息的机制
公开(公告)号：US5848279A
公开(公告)日：1998-12-08
申请号：US777308
申请日：1996-12-27
申请人： William S. Wu , Mani Azimi , Stephen Pawlowski , Daniel G. Lau , Muthurajan Jayakumar
发明人： William S. Wu , Mani Azimi , Stephen Pawlowski , Daniel G. Lau , Muthurajan Jayakumar
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.
摘要翻译： I / O代理通过芯片组将中断消息传递到连接到多个处理器的系统总线。中断消息包括事务类型和目标标识。系统总线上的服务处理器将目的地标识与其自己的标识相匹配，以确定它是否是中断消息的预期接收者。 I / O代理将与中断相关的数据写入芯片组内的缓冲队列。在发送中断消息之前，芯片组会自动将缓冲队列的内容刷新到主存储器。中断传送机制避免了芯片组和I / O代理之间的握手操作的复杂性和延迟。

3. 发明授权

US06418496B2 System and apparatus including lowest priority logic to select a processor to receive an interrupt message 失效
标题翻译：包括用于选择处理器以接收中断消息的最低优先级逻辑的系统和装置
公开(公告)号：US06418496B2
公开(公告)日：2002-07-09
申请号：US08988233
申请日：1997-12-10
申请人： Stephen S. Pawlowski , Daniel G. Lau
发明人： Stephen S. Pawlowski , Daniel G. Lau
IPC分类号： G06F1324
CPC分类号： G06F13/26
摘要： One embodiment of the invention includes an apparatus, such as a bridge, for use in connection a with computer system. The apparatus includes remote priority capture logic to hold task priority data indicative of a task priority of each processor in the computer system that is available for lowest priority interrupt destination arbitration (LPIDA). The apparatus also includes lowest priority logic to perform the LPIDA to select processor in the computer system is to receive an interrupt message based on contents of the remote priority capture logic. Another embodiment of the invention includes a multi-processor system having processors and a processor bus coupled to the processors. The system includes remote priority capture logic to hold task priority data indicative of a task priority of the processors while they are available for lowest priority interrupt destination arbitration (LPIDA). The system also includes lowest priority logic to perform the LPIDA to select which of the processors is to receive an interrupt message based on contents of the remote priority capture logic, the interrupt message being provided to the processor through the processor bus.
摘要翻译：本发明的一个实施例包括用于连接计算机系统的装置，例如桥。该设备包括远程优先级捕获逻辑，以保存指示可用于最低优先级中断目的地仲裁（LPIDA）的计算机系统中的每个处理器的任务优先级的任务优先级数据。该装置还包括执行LPIDA以选择计算机系统中的处理器的最低优先级逻辑是基于远程优先级捕获逻辑的内容接收中断消息。本发明的另一实施例包括具有处理器和耦合到处理器的处理器总线的多处理器系统。该系统包括远程优先级捕获逻辑，以保持指示处理器的任务优先级的任务优先级数据，同时它们可用于最低优先级中断目的地仲裁（LPIDA）。该系统还包括执行LPIDA的最低优先级逻辑，以根据远程优先级捕获逻辑的内容选择哪些处理器接收中断消息，该中断消息通过处理器总线提供给处理器。

4. 发明授权

US5958037A Apparatus and method for identifying the features and the origin of a computer microprocessor 失效
标题翻译：用于识别计算机微处理器的特征和原点的装置和方法
公开(公告)号：US5958037A
公开(公告)日：1999-09-28
申请号：US023916
申请日：1993-02-26
申请人： Robert S. Dreyer , William M. Corwin , Donald B. Alpert , Tsu-Hua Wang , Daniel G. Lau , Frederick J. Pollack
发明人： Robert S. Dreyer , William M. Corwin , Donald B. Alpert , Tsu-Hua Wang , Daniel G. Lau , Frederick J. Pollack
IPC分类号： G06F15/78 , G06F1/00 , G06F9/30 , G06F9/445 , G06F11/00 , G06F21/00 , G06F9/22
CPC分类号： G06F21/73 , G06F11/006 , G06F9/30003 , G06F9/328 , G06F9/44505 , G06F2207/7219
摘要： A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.
摘要翻译：一种用于提供至少两种类型的识别信息的多级识别装置和方法，所述识别信息包括用于识别微处理器的来源的第一类型和可用的识别信息的级数，以及用于识别家族的第二类型，模型，步进ID，以及微处理器的功能。该装置包括用于存储识别微处理器原点的标记串的第一存储元件。该装置还包括用于存储包括特定识别微处理器的数据字段的其它微处理器ID数据的第二存储器元件。该装置包括用于执行读取指示字符串或微处理器ID数据的ID指令的控制逻辑，这取决于预选类型。无论读取哪个识别信息，它被存储在一个或多个通用寄存器中，以供程序员选择读取。该方法在微处理器运行时随时可用。

5. 发明授权

US06219741B1 Transactions supporting interrupt destination redirection and level triggered interrupt semantics 失效
标题翻译：事务支持中断目标重定向和电平触发中断语义
公开(公告)号：US06219741B1
公开(公告)日：2001-04-17
申请号：US08988232
申请日：1997-12-10
申请人： Stephen S. Pawlowski , Daniel G. Lau , Kimberly C. Weier
发明人： Stephen S. Pawlowski , Daniel G. Lau , Kimberly C. Weier
IPC分类号： G06F1324
CPC分类号： G06F13/26
摘要： In one embodiment, the invention includes an apparatus, such as a bridge, for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus a task priority update transaction including data representative of a task priority designation of a processor of the computer system, and to provide a signal responsive thereto. The apparatus also includes remote priority capture logic to receive the signal responsive to the task priority update transaction and update contents of the remote priority capture logic in response thereto. In another embodiment, the invention includes an apparatus for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus an end-of-interrupt (EOI) transactions and to provide an EOI signal responsive thereto. The apparatus also includes an interrupt controller including a table having a state bit that is set in response to the interrupt controller receiving an interrupt signal and reset in response to the interrupt controller receiving the EOI signal.
摘要翻译：在一个实施例中，本发明包括与具有处理器总线的计算机系统一起使用的装置，例如桥接器。该装置包括解码逻辑，以通过处理器总线接收包括表示计算机系统的处理器的任务优先级指定的数据的任务优先级更新事务，并提供响应于此的信号。该装置还包括远程优先捕获逻辑，以响应于任务优先级更新事务接收信号，并响应于此更新远程优先级捕获逻辑的内容。在另一个实施例中，本发明包括一种与具有处理器总线的计算机系统一起使用的装置。该装置包括解码逻辑，以通过处理器总线接收中断终止（EOI）事务，并响应于此提供EOI信号。该装置还包括一个中断控制器，该中断控制器包括具有响应于中断控制器接收到中断信号而被设置并根据中断控制器接收到EOI信号而复位的状态位的表。

6. 发明授权

US5794066A Apparatus and method for identifying the features and the origin of a computer microprocessor 失效
公开(公告)号：US5794066A
公开(公告)日：1998-08-11
申请号：US644678
申请日：1996-05-07
申请人： Robert S. Dreyer , William M. Corwin , Tsu-Hua Wang , Daniel G. Lau , Frederick J. Pollack
发明人： Robert S. Dreyer , William M. Corwin , Tsu-Hua Wang , Daniel G. Lau , Frederick J. Pollack
IPC分类号： G06F15/78 , G06F1/00 , G06F9/30 , G06F9/445 , G06F11/00 , G06F21/00 , G06F11/30
CPC分类号： G06F21/73 , G06F11/006 , G06F9/30003 , G06F9/328 , G06F9/44505 , G06F2207/7219
摘要： A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

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