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1. 发明授权

US09075138B2 Efficient pulse Doppler radar with no blind ranges, range ambiguities, blind speeds, or Doppler ambiguities 有权
标题翻译：高效脉搏多普勒雷达，无盲区，范围模糊度，盲速度或多普勒模糊度
公开(公告)号：US09075138B2
公开(公告)日：2015-07-07
申请号：US13453195
申请日：2012-04-23
申请人： William S. Song
发明人： William S. Song
IPC分类号： G01S13/08 , G01S13/22 , G01S13/28 , G01S13/58
CPC分类号： G01S13/22 , G01S13/288 , G01S13/582
摘要： A Doppler radar system that avoids blind ranges, range ambiguities, blind speed and/or Doppler ambiguities. Pulse width, repetition interval and pulse type are varied from pulse to pulse within a coherent processing interval.
摘要翻译：多普勒雷达系统避免盲区，范围模糊，盲速和/或多普勒模糊。脉冲宽度，重复间隔和脉冲类型在相干处理间隔内从脉冲到脉冲变化。

2. 发明申请

US20110307685A1 Processor for Large Graph Algorithm Computations and Matrix Operations 有权
标题翻译：大图算法和矩阵运算的处理器
公开(公告)号：US20110307685A1
公开(公告)日：2011-12-15
申请号：US13153490
申请日：2011-06-06
申请人： William S. Song
发明人： William S. Song
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/3001 , G06F17/10 , G06F17/16
摘要： A multiprocessor system and method for performing matrix operations includes multiple processors cooperatively performing a sparse matrix operation. Distributed among the processors are non-zero matrix elements of first and second sparse matrices. Mapped across the processors are the matrix elements of a results matrix. Each processor receives, from the other processors, non-zero matrix elements of the first matrix that had been distributed to those other processors and generates partial results based on the received non-zero matrix elements of the first matrix and on the non-zero matrix elements of the second matrix distributed to that processor. Each processor receives those partial results generated by other processors and associated with the matrix elements of the results matrix mapped to that processor. Each processor generates a final value for each matrix element of the results matrix mapped to that processor based on the partial results generated by that processor and on the partial results received from the other processors associated with that matrix element of the results matrix.
摘要翻译：用于执行矩阵运算的多处理器系统和方法包括协同执行稀疏矩阵运算的多个处理器。在处理器之间分布的是第一和第二稀疏矩阵的非零矩阵元素。跨处理器的映射是结果矩阵的矩阵元素。每个处理器从其他处理器接收已经分配给那些其他处理器的第一矩阵的非零矩阵元素，并且基于所接收的第一矩阵的非零矩阵元素和非零矩阵生成部分结果分配给该处理器的第二矩阵的元素。每个处理器接收由其他处理器生成并与映射到该处理器的结果矩阵的矩阵元素相关联的部分结果。每个处理器基于由该处理器生成的部分结果以及从与结果矩阵的该矩阵元素相关联的其他处理器接收的部分结果，生成映射到该处理器的结果矩阵的每个矩阵元素的最终值。

3. 发明授权

US08819272B2 Multiprocessor communication networks 有权
标题翻译：多处理器通信网络
公开(公告)号：US08819272B2
公开(公告)日：2014-08-26
申请号：US12703938
申请日：2010-02-11
申请人： William S. Song
发明人： William S. Song
IPC分类号： G06F15/173
CPC分类号： H04L47/125 , G06F15/17381 , G06F15/17387 , H04L45/06 , H04L45/12 , H04L45/24
摘要： A parallel multiprocessor system includes a packet-switching communication network comprising a plurality of processor nodes operating concurrently in parallel. Each processor node generates messages to be sent simultaneously to a plurality of other processor nodes in the communication network. Each message is divided into a plurality of packets having a common destination processor node. Each processor node has an arbiter that determines an order in which to forward the packets onto the network toward their destination processor nodes and a network interface that sends the packets onto the network in accordance with the determined order. The determined order operates to substantially avoid sending consecutive packets from a given source processor node to a given destination processor node and to randomize the destination processor nodes of those packets presently traversing the communication network.
摘要翻译：并行多处理器系统包括分组交换通信网络，其包括并行操作的多个处理器节点。每个处理器节点产生要同时发送到通信网络中的多个其他处理器节点的消息。每个消息被分成具有公共目的地处理器节点的多个分组。每个处理器节点具有仲裁器，该仲裁器确定将数据包转发到网络上的目的地处理器节点的顺序和根据确定的顺序将分组发送到网络的网络接口。确定的顺序操作以基本上避免将给定源处理器节点的连续分组发送到给定的目的地处理器节点，并使目前遍历通信网络的分组的目的地处理器节点随机化。

4. 发明授权

US08751556B2 Processor for large graph algorithm computations and matrix operations 有权
标题翻译：用于大图算法计算和矩阵运算的处理器
公开(公告)号：US08751556B2
公开(公告)日：2014-06-10
申请号：US13153490
申请日：2011-06-06
申请人： William S. Song
发明人： William S. Song
IPC分类号： G06F17/16
CPC分类号： G06F9/3001 , G06F17/10 , G06F17/16
摘要： A multiprocessor system and method for performing matrix operations includes multiple processors cooperatively performing a sparse matrix operation. Distributed among the processors are non-zero matrix elements of first and second sparse matrices. Mapped across the processors are the matrix elements of a results matrix. Each processor receives, from the other processors, non-zero matrix elements of the first matrix that had been distributed to those other processors and generates partial results based on the received non-zero matrix elements of the first matrix and on the non-zero matrix elements of the second matrix distributed to that processor. Each processor receives those partial results generated by other processors and associated with the matrix elements of the results matrix mapped to that processor. Each processor generates a final value for each matrix element of the results matrix mapped to that processor based on the partial results generated by that processor and on the partial results received from the other processors associated with that matrix element of the results matrix.
摘要翻译：用于执行矩阵运算的多处理器系统和方法包括协同执行稀疏矩阵运算的多个处理器。在处理器之间分布的是第一和第二稀疏矩阵的非零矩阵元素。跨处理器的映射是结果矩阵的矩阵元素。每个处理器从其他处理器接收已经分配给那些其他处理器的第一矩阵的非零矩阵元素，并且基于所接收到的第一矩阵的非零矩阵元素和非零矩阵生成部分结果分配给该处理器的第二矩阵的元素。每个处理器接收由其他处理器生成并与映射到该处理器的结果矩阵的矩阵元素相关联的部分结果。每个处理器基于由该处理器生成的部分结果以及从与结果矩阵的该矩阵元素相关联的其他处理器接收的部分结果，生成映射到该处理器的结果矩阵的每个矩阵元素的最终值。

5. 发明授权

US08508395B2 Time varying quantization-based linearity enhancement of signal converters and mixed-signal systems 有权
标题翻译：信号转换器和混合信号系统的时变量化线性增强
公开(公告)号：US08508395B2
公开(公告)日：2013-08-13
申请号：US13182260
申请日：2011-07-13
申请人： William S. Song
发明人： William S. Song
IPC分类号： H03M1/20
CPC分类号： H03M1/12 , H03M1/0626 , H03M1/0639 , H03M1/0641 , H03M1/66
摘要： A signal-linearization system and method reduces nonlinear distortions in a digitized signal generated by an analog-to-digital converter (ADC) when converting an analog input signal from analog to digital form. A signal adder adds a dither waveform to the analog input signal. An ADC includes sample-and-hold (S/H) circuitry and quantizer circuitry. The ADC converts the analog input signal with the added dither waveform into a digitized signal. The dither waveform operates to suppress nonlinear distortions attributed to the quantizer circuitry. A linearizer processor performs nonlinear equalization (NLEQ) on the digitized signal to suppress nonlinear distortions attributed to the S/H circuitry. A dither waveform removal module removes a digital counterpart of the dither waveform from the digitized signal.
摘要翻译：当将模拟输入信号从模拟形式转换成数字形式时，信号线性化系统和方法减少由模数转换器（ADC）产生的数字化信号中的非线性失真。信号加法器将抖动波形加到模拟输入信号上。 ADC包括采样保持（S / H）电路和量化器电路。 ADC将添加的抖动波形的模拟输入信号转换为数字化信号。抖动波形用于抑制归因于量化器电路的非线性失真。线性化处理器对数字化信号执行非线性均衡（NLEQ）以抑制归因于S / H电路的非线性失真。抖动波形去除模块从数字化信号中去除抖动波形的数字对应物。

6. 发明授权

US07480689B2 Systolic de-multiplexed finite impulse response filter array architecture for linear and non-linear implementations 失效
标题翻译：用于线性和非线性实现的收缩解复用有限脉冲响应滤波器阵列架构
公开(公告)号：US07480689B2
公开(公告)日：2009-01-20
申请号：US10993076
申请日：2004-11-19
申请人： William S. Song
发明人： William S. Song
IPC分类号： G06F17/10
CPC分类号： H03H17/06 , H03H2220/06
摘要： Described is a finite impulse filter response (FIR) filter for use by signal processors. A demultiplexer receives input data samples at an input data rate. The FIR filter includes a plurality of computational units arranged in a systolic array of taps and phases. Each computational unit operates at an array clock rate that is slower than the input data rate. During each array clock cycle, the phases produce a plurality of output data samples that provides an output data rate equal to the input data rate. The FIR filters can thus support an output data rate equal to the input data rate although the input data rate exceeds the maximum clock speed of the processor. The FIR filter can also operate at a reduced array clock speed, while continuing to produce an output data rate equal to the input data rate, to increase the power efficiency of the processor.
摘要翻译：描述了一种用于信号处理器的有限脉冲滤波器响应（FIR）滤波器。解复用器以输入数据速率接收输入数据采样。 FIR滤波器包括多个计算单元，布置在抽头和相位的收缩阵列中。每个计算单元以比输入数据速率慢的阵列时钟速率工作。在每个阵列时钟周期期间，相位产生多个输出数据样本，其提供等于输入数据速率的输出数据速率。因此，尽管输入数据速率超过处理器的最大时钟速度，但是FIR滤波器因此可以支持等于输入数据速率的输出数据速率。 FIR滤波器也可以以降低的阵列时钟速度工作，同时继续产生等于输入数据速率的输出数据速率，以提高处理器的功率效率。

7. 发明授权

US4964126A Fault tolerant signal processing machine and method 失效
标题翻译：容错信号处理机及方法
公开(公告)号：US4964126A
公开(公告)日：1990-10-16
申请号：US251572
申请日：1988-09-30
申请人： Bruce R. Musicus , William S. Song
发明人： Bruce R. Musicus , William S. Song
IPC分类号： G06F11/08 , G06F11/16
CPC分类号： G06F11/08 , G06F11/16
摘要： The machine includes a plurality of processors each performing identical linear processing operations on its input signal. At least one checksum processor is provided to perform the same linear processing operation as the plurality of processors. Computing apparatus using inexact arithmetic forms a linear combination of the input signals to form an input checksum signal and for operating on the input checksum signal with the checksum processor to generate a processed input checksum signal. The same linear combination of the outputs of the plurality of processors is formed to produce an output checksum signal and the output checksum signal is compared with the processed input checksum signal to produce an error syndrome. A generalized likelihood ratio test is formed from the error syndrome for assessing a likeliest failure hypothesis. The fault tolerant multiprocessor architecture exploits computational redundancy to provide a very high level of fault tolerance with a small amount of hardware redundancy. The architecture uses weighted checksum techniques, and is suited for linear, digital, or analog signal processing.
摘要翻译：该机器包括多个处理器，每个处理器对其输入信号执行相同的线性处理操作。提供至少一个校验和处理器以执行与多个处理器相同的线性处理操作。使用不精确算术的计算装置形成输入信号的线性组合以形成输入校验和信号，并且利用校验和处理器对输入校验和信号进行操作，以产生经处理的输入校验和信号。形成多个处理器的输出的相同的线性组合以产生输出校验和信号，并将输出校验和信号与经处理的输入校验和信号进行比较以产生误差综合征。广义似然比检验由误差综合征形成，用于评估最有效的失败假说。容错多处理器体系结构利用计算冗余，以少量硬件冗余提供非常高级别的容错能力。该架构使用加权校验和技术，适用于线性，数字或模拟信号处理。

8. 发明授权

US08259003B2 High duty cycle radar with near/far pulse compression interference mitigation 有权
标题翻译：具有近/远脉冲压缩干扰减轻的高占空比雷达
公开(公告)号：US08259003B2
公开(公告)日：2012-09-04
申请号：US12780221
申请日：2010-05-14
申请人： William S. Song
发明人： William S. Song
IPC分类号： G01S13/32
CPC分类号： G01S7/292 , G01S7/023 , G01S13/282
摘要： In conventional pulse compression processing, sidelobes from strong return signals may hide correlation peaks associated with weaker return signals. Example embodiments include methods of mitigating this near/far interference by weighting a received return signal or corresponding reference signal based the return signal's time of arrival, then performing pulse compression using the weighted signal to produce a correlation peak that is not hidden by sidelobes from another return. Multi-frequency processing can also be used to reduce the pulse width of the transmitted pulses and received return signals, thereby mitigating near/far interference by decreasing the overlap between signals from nearby targets. Weighting can be combined with multi-frequency pulse transmission and reception to further enhance the fidelity of the processed correlation peak. Weighting and multi-frequency processing also enable higher duty cycles than are possible with conventional pulse compression radars.
摘要翻译：在常规脉冲压缩处理中，来自强返回信号的旁瓣可隐藏与较弱返回信号相关的相关峰值。示例性实施例包括通过基于返回信号的到达时间对接收到的返回信号或相应的参考信号进行加权来减轻该近/远的干扰的方法，然后使用加权信号执行脉冲压缩以产生不被来自另一个的旁瓣隐藏的相关峰返回。多频处理也可用于减少发射脉冲和接收的返回信号的脉冲宽度，从而通过减少来自附近目标的信号之间的重叠来减轻近/远的干扰。加权可以与多频脉冲发射和接收相结合，以进一步提高处理相关峰值的保真度。加权和多频处理也可以实现比传统的脉冲压缩雷达更高的占空比。

9. 发明授权

US07142607B2 Efficient subband channelizer and subband combiner with oversampled subbands 失效
公开(公告)号：US07142607B2
公开(公告)日：2006-11-28
申请号：US10156066
申请日：2002-05-28
申请人： William S. Song
发明人： William S. Song
IPC分类号： H04L27/28
CPC分类号： H04L5/06 , H03H17/0266
摘要： A subband channelizer that includes a demultiplexer that receives input samples of a signal and distributes the input samples to a plurality of channelizer filter banks. A Fourier transform module that receives outputs from the plurality of channelizer filter banks and performs Fourier transformation on each of the outputs of the channelizer filters, and outputs a plurality of Fourier signals. A plurality of multiplier modules that receive the Fourier signals, and each of the Fourier signals is multiplied with an exponential value assigned to each of the plurality of multiplier modules to produce oversampled subbands. A combiner for generating a wideband signal from a plurality of input subbands is also included.

10. 发明授权

US6118396A Optically sampling, demultiplexing, and A/D converting system with improved speed 失效
标题翻译：光学采样，解复用和A / D转换系统，提高速度
公开(公告)号：US6118396A
公开(公告)日：2000-09-12
申请号：US998304
申请日：1997-12-24
申请人： William S. Song
发明人： William S. Song
IPC分类号： H03M1/12 , H03M1/36 , G02F7/00
CPC分类号： H03M1/1215 , G02F7/00 , H03M1/368
摘要： An ultra-fast electrooptic analog-to-digital converter is described. The A/D converter includes an electrooptic modulator that generates a modulated light beam from an incident light beam in response to an applied modulation signal. An optical demultiplexer is positioned to receive the modulated light beam. The optical input of a respective one of a plurality of photodetectors is optically coupled to a respective one of a plurality of demultiplexed modulated light beams. Each of the plurality of photodetectors generates an electrical signal in response to an intensity of the demultiplexed modulated light beam that is coupled to its optical input. A plurality of charge comparators compares electrical signals generated in response to the intensities of the demultiplexed modulated light beam to a reference signal. The output of each of the plurality of charge comparators generates a digital representation of the incident light beam.
摘要翻译：描述了一种超快速电光模拟 - 数字转换器。 A / D转换器包括电光调制器，其响应于施加的调制信号从入射光束产生调制光束。光解复用器被定位成接收调制光束。多个光电检测器中的相应一个的光输入被光耦合到多个解复用的调制光束中的相应一个。多个光电检测器中的每一个响应于被耦合到其光输入的解复用的调制光束的强度而产生电信号。多个充电比较器将响应于解复用的调制光束的强度产生的电信号与参考信号进行比较。多个电荷比较器中的每一个的输出产生入射光束的数字表示。

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