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1. 发明授权

US5497103A Test apparatus for circuitized substrate 失效
标题翻译：电路化基板试验装置
公开(公告)号：US5497103A
公开(公告)日：1996-03-05
申请号：US378348
申请日：1995-01-25
申请人： William S. Ebert , David E. Engle , Kishor V. Desai , Thomas G. Macek
发明人： William S. Ebert , David E. Engle , Kishor V. Desai , Thomas G. Macek
IPC分类号： G01R1/04 , G01R1/073
CPC分类号： G01R1/0408 , G01R1/07314
摘要： A test apparatus and method for testing circuitized substrates such as printed circuit boards or ceramic substrates having one or more chips thereon. The apparatus includes one substrate (e.g., printed circuit board) located on a base and adapted for having another circuitized substrate (e.g., flexible circuit) positioned thereon and electrically coupled to conductive elements (e.g., copper pads) thereof. Elastomeric members may be used to force the flexible circuit against the conductors of the substrate being tested, this substrate positioned either within or upon a cover which is located over the flexible circuit and which assists in compressing the flexible circuit against the printed circuit board's conductive elements to assure positive connection therewith. The cover may also include elastomeric members to facilitate such connection and a pivotal arm for being actuated to engage the substrate being tested. Positioning as well as relative quick separation (removal) of the substrate is attainable upon completion of the testing.
摘要翻译：一种用于测试诸如印刷电路板或其上具有一个或多个芯片的陶瓷基板的电路化基板的测试装置和方法。该装置包括一个位于基座上的基片（例如，印刷电路板），并且适于使另一电路化基底（例如柔性电路）位于其上并电耦合到其导电元件（例如铜垫）上。可以使用弹性构件来将柔性电路强制抵抗被测试的衬底的导体，该衬底位于柔性电路之上的覆盖物内或之上，并有助于将柔性电路压靠印刷电路板的导电元件以确保与其的正向连接。盖子还可以包括弹性体构件以促进这种连接以及用于被致动以接合被测试的衬底的枢转臂。完成测试后可以进行基板的定位和相对快速的分离（去除）。

2. 发明授权

US5137456A High density, separable connector and contact for use therein 失效
标题翻译：高密度，可分离的连接器和接触件用于其中
公开(公告)号：US5137456A
公开(公告)日：1992-08-11
申请号：US787285
申请日：1991-11-04
申请人： Kishor V. Desai , Thomas G. Macek , Maganlal S. Patel , Edwin L. Thomas
发明人： Kishor V. Desai , Thomas G. Macek , Maganlal S. Patel , Edwin L. Thomas
IPC分类号： H01R4/50 , G01R31/28 , H01R11/01 , H01R12/52 , H01R12/71 , H01R13/24 , H05K1/14
CPC分类号： H01R12/714 , H01R12/52
摘要： An electrical connector for interconnecting a pair of circuit members (e.g., printed circuit boards) wherein the connector includes a plurality of electrical contacts, these contacts including at least one semi-spherical end portion for engaging a respective conductor on one of the circuit members. Significantly, the semi-spherical end portion is capable of moving in two different directions of rotation during such engagement to provide an effective wiping motion against the surfaces of the member's conductor. In one embodiment, the connector includes contacts with opposed, semi-spherical end portions, while in another embodiment, a singular semi-spherical end portion is taught.
摘要翻译：一种用于互连一对电路构件（例如印刷电路板）的电连接器，其中连接器包括多个电触点，这些触点包括至少一个半球形端部，用于与一个电路构件上的相应导体接合。重要的是，半球形端部能够在这种接合期间在两个不同的旋转方向上移动，以对构件导体的表面提供有效的擦拭运动。在一个实施例中，连接器包括具有相对的半球形端部的触点，而在另一个实施例中，教导了单个半球形端部。

3. 发明授权

US5259781A Electrical connector alignment and actuation assembly 失效
标题翻译：电气连接器对准和驱动组件
公开(公告)号：US5259781A
公开(公告)日：1993-11-09
申请号：US977946
申请日：1992-11-18
申请人： John G. Baumberger , James R. Bentlage , Fletcher W. Chapin , Kishor V. Desai , Alan D. Knight , Thomas G. Macek
发明人： John G. Baumberger , James R. Bentlage , Fletcher W. Chapin , Kishor V. Desai , Alan D. Knight , Thomas G. Macek
IPC分类号： H01R12/71 , H01R13/24 , H01R13/621 , H05K7/10 , H01R13/627
CPC分类号： H01R13/2435 , H01R12/714 , H01R13/6215 , H05K7/1069
摘要： A connector assembly has a plurality of electrical circuit members and interposer frames with resilient contact members pressed together by a centrally located actuation screw. The actuation screw is supported within a threaded hole in an actuation bar on one side of one of the circuit members. Turning the actuation screw in its threaded hole causes various parts of the connector assembly to be pressed together simultaneously under an evenly distributed load. A load distribution plate located between the actuation screw and the nearest circuit member reduces the bending stresses in that circuit member. Alignment bushings and pins extending through openings in the circuit members maintain the various parts of the assembly in proper alignment while the actuation screw is being turned.
摘要翻译：连接器组件具有多个电路构件和具有弹性接触构件的介入框架，弹性接触构件通过位于中心的致动螺钉压在一起。致动螺钉被支撑在一个电路构件的一侧上的致动杆的螺纹孔内。在其螺纹孔中转动致动螺钉使得连接器组件的各个部件在均匀分布的负载下同时被压在一起。位于致动螺钉和最近的电路部件之间的负载分配板降低了该电路部件中的弯曲应力。对准衬套和延伸穿过电路构件中的开口的销在保持致动螺丝转动的同时保持组件的各个部分正确对准。

4. 发明授权

US08772946B2 Reduced stress TSV and interposer structures 有权
标题翻译：减少应力TSV和插入结构
公开(公告)号：US08772946B2
公开(公告)日：2014-07-08
申请号：US13492064
申请日：2012-06-08
申请人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
发明人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/34 , H01L21/76841 , H01L21/76883 , H01L21/76885 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05558 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/1134 , H01L2224/1147 , H01L2224/13082 , H01L2224/13083 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/13565 , H01L2224/32105 , H01L2924/00011 , H01L2924/01322 , H01L2924/07811 , H01L2924/12042 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/81805
摘要： A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.
摘要翻译：部件可以包括在基板的开口内延伸的基板和导电通孔。基底可以具有第一和第二相对表面。开口可以从第一表面延伸到第二表面，并且可以具有远离第一表面延伸的内壁。电介质材料可以在内壁暴露。导电通孔可以在邻近第一表面的开口内限定释放通道。释放通道可以具有在与第一表面平行且在五微米以内的平面的方向上离内壁的第一距离内的边缘，第一距离是最小宽度的一微米和百分之五的最小宽度在飞机上开了边缘可以沿着内壁延伸以跨越内壁的圆周的至少百分之五。

5. 发明申请

US20130328186A1 REDUCED STRESS TSV AND INTERPOSER STRUCTURES 有权
标题翻译：减少应力TSV和间接结构
公开(公告)号：US20130328186A1
公开(公告)日：2013-12-12
申请号：US13492064
申请日：2012-06-08
申请人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
发明人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
IPC分类号： H01L23/48 , H01L21/28 , H01L23/498
CPC分类号： H01L23/34 , H01L21/76841 , H01L21/76883 , H01L21/76885 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05558 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/1134 , H01L2224/1147 , H01L2224/13082 , H01L2224/13083 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/13565 , H01L2224/32105 , H01L2924/00011 , H01L2924/01322 , H01L2924/07811 , H01L2924/12042 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/81805
摘要： A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.
摘要翻译：部件可以包括在基板的开口内延伸的基板和导电通孔。基底可以具有第一和第二相对表面。开口可以从第一表面延伸到第二表面，并且可以具有远离第一表面延伸的内壁。电介质材料可以在内壁暴露。导电通孔可以在邻近第一表面的开口内限定释放通道。释放通道可以具有在与第一表面平行且在五微米以内的平面的方向上离内壁的第一距离内的边缘，第一距离是最小宽度的一微米和百分之五的最小宽度在飞机上开了边缘可以沿着内壁延伸以跨越内壁的圆周的至少百分之五。

6. 发明授权

US07727781B2 Manufacture of devices including solder bumps 有权
标题翻译：制造包括焊料凸点的器件
公开(公告)号：US07727781B2
公开(公告)日：2010-06-01
申请号：US12220182
申请日：2008-07-22
申请人： Joze Eura Antol , Kishor V. Desai , John William Osenbach , Brian Thomas Vaccaro
发明人： Joze Eura Antol , Kishor V. Desai , John William Osenbach , Brian Thomas Vaccaro
IPC分类号： G01L31/26 , H01L21/66
CPC分类号： H05K3/3452 , H05K3/3457 , H05K2201/099 , H05K2203/0271 , H05K2203/162
摘要： Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.
摘要翻译：焊接接头（例如印刷电路板焊盘处的接头）的典型测试尚未被证明完全可以预测这种接头的最终性能。已经发现，这种缺乏可靠性至少部分地是由于这些焊盘在测试期间失去与下面的衬底的粘附或分层的倾向。相比之下，这种情况并不是典型的设备使用期间引起的现象。为了消除这种不可靠性的原因，测试结构与制造设备批次一起进行。使用相同的焊盘处理，并且焊盘尺寸在测试结构中大大扩大。测试结构用于预测批次中的设备的性能，然后相应地处理批次。

7. 发明授权

US06552266B2 High performance chip packaging and method 有权
公开(公告)号：US06552266B2
公开(公告)日：2003-04-22
申请号：US09770913
申请日：2001-01-26
申请人： Timothy F. Carden , Glenn O. Dearing , Kishor V. Desai , Stephen R. Engle , Randall Stutzman , George H. Thiel
发明人： Timothy F. Carden , Glenn O. Dearing , Kishor V. Desai , Stephen R. Engle , Randall Stutzman , George H. Thiel
IPC分类号： H01L2302
CPC分类号： H01L23/10 , H01L21/50 , H01L2224/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01078 , H01L2924/15311 , H01L2924/16195 , Y10T29/4913 , Y10T29/49144 , Y10T29/49149 , Y10T29/49169
摘要： A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board.

8. 发明授权

US06266249B1 Semiconductor flip chip ball grid array package 有权
标题翻译：半导体倒装芯片球栅阵列封装
公开(公告)号：US06266249B1
公开(公告)日：2001-07-24
申请号：US09375835
申请日：1999-08-16
申请人： Kishor V. Desai , Sunil Patel , Ramaswamy Ranganathan
发明人： Kishor V. Desai , Sunil Patel , Ramaswamy Ranganathan
IPC分类号： H05K118
CPC分类号： H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package is present along with an associated method. The package comprises a substrate with a top surface and a bottom surface, the substrate having a plurality of electrically conductive vias extending from the top surface of the substrate to the bottom surface of the substrate. A semiconductor device having an active surface, the active surface having a plurality of bonding pads, is attached to the substrate by an adhesive that bas holes that align with the vias. The vias are also aligned with the bonding pads. Solder serves to electrically and mechanically couple each of the bonding pads with a corresponding via. Each of the vias, in turn, is coupled to a solder ball formed on the bottom of the substrate.
摘要翻译：存在半导体封装以及相关方法。该封装包括具有顶表面和底表面的衬底，该衬底具有从衬底的顶表面延伸到衬底的底表面的多个导电通孔。具有活性表面的半导体器件，具有多个接合焊盘的活性表面通过与通孔对准的基底孔的粘合剂附着到基底上。通孔也与焊盘对准。焊料用于将每个焊盘与相应的通孔电连接和机械耦合。每个通孔又连接到形成在基底的底部上的焊球。

9. 发明授权

US06655020B2 Method of packaging a high performance chip 失效
标题翻译：封装高性能芯片的方法
公开(公告)号：US06655020B2
公开(公告)日：2003-12-02
申请号：US09770915
申请日：2001-01-26
申请人： Timothy F. Carden , Glenn O. Dearing , Kishor V. Desai , Stephen R. Engle , Randall Stutzman , George H. Thiel
发明人： Timothy F. Carden , Glenn O. Dearing , Kishor V. Desai , Stephen R. Engle , Randall Stutzman , George H. Thiel
IPC分类号： H05K334
CPC分类号： H01L23/10 , H01L21/50 , H01L2224/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01078 , H01L2924/15311 , H01L2924/16195 , Y10T29/4913 , Y10T29/49144 , Y10T29/49149 , Y10T29/49169
摘要： A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener is disclosed. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board is disclosed.
摘要翻译：公开了一种芯片载体封装，其包括通过可回流接合材料附接到加强件的盖板。此外，可以包括在盖板和芯片本身之间的导热和导电的接合材料。还公开了一种包括对准装置以帮助正确对准加强件上的盖板的芯片封装。此外，一种包装芯片的方法，包括在盖板和加强体之间提供可回流材料，用于将盖板附接到加强件，并且将托架附接到电子电路板上同时将盖板附接到加强件，披露

10. 发明授权

US06452116B2 Use of blind vias for soldered interconnections between substrates and printed wiring boards 有权
标题翻译：对基板和印刷电路板之间的焊接互连使用盲孔
公开(公告)号：US06452116B2
公开(公告)日：2002-09-17
申请号：US09796389
申请日：2001-02-28
申请人： Gregg J. Armezzani , Kishor V. Desai , Jeffrey S. Perkins , John J. Pessarchick
发明人： Gregg J. Armezzani , Kishor V. Desai , Jeffrey S. Perkins , John J. Pessarchick
IPC分类号： H01R909
CPC分类号： H05K1/112 , H05K1/0298 , H05K2201/09227 , H05K2201/09509 , H05K2201/10734 , Y10T29/49117 , Y10T29/49126 , Y10T29/49144
摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of placing one or more blind vias in a first substrate positioned on top of a first conductor; placing one or more blind vias in a second substrate positioned under a second conductor; attaching one or more signal lines to one or more of the one or more blind vias; and assembling ball grid array components such that the first conductor is electrically connected to the second conductor. Also claimed is an electronic circuit package incorporating the blind vias for electrical connection between layers in accordance with the present invention.
摘要翻译：提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：将一个或多个盲孔放置在位于第一导体顶部的第一衬底中; 将一个或多个盲孔放置在位于第二导体下方的第二衬底中; 将一个或多个信号线附接到所述一个或多个盲孔中的一个或多个; 以及组装球栅阵列部件，使得第一导体电连接到第二导体。还要求保护的是一种电子电路封装，其包括用于根据本发明的层之间的电连接的盲孔。

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