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1. 发明申请

US20050212144A1 Stacked die for inclusion in standard package technology 审中-公开
标题翻译：堆叠模具包含在标准封装技术中
公开(公告)号：US20050212144A1
公开(公告)日：2005-09-29
申请号：US10809720
申请日：2004-03-25
申请人： William Rugg , Robert Warren , Chau-Chin Low
发明人： William Rugg , Robert Warren , Chau-Chin Low
IPC分类号： H01L25/065 , H01L25/18 , H01L29/40
CPC分类号： H01L25/0657 , H01L25/0652 , H01L25/18 , H01L2224/48145 , H01L2225/06506 , H01L2225/06527 , H01L2225/06562 , H01L2924/14 , H01L2924/00012
摘要： Disclosed is a method and apparatus for stacking dice including multi-chip packaging with additional non stacked dice. The stacked dice have at least one electrical connection located on a single surface and oriented in the same direction when stacked. These dice are stacked, offset and coupled electrically. In an embodiment, the stacked dice have a buffer function, such as an SDRAM device, and are included in a multi-chip package (MCP) with an additional die including a channel function and a controller function thereon. The dice are packaged in a single package for placement on a printed circuit board for use in a storage device such as a disc drive.
摘要翻译：公开了一种用于堆叠包括多芯片封装的骰子的附加非堆叠骰子的方法和装置。堆叠的骰子具有位于单个表面上的至少一个电连接并且在堆叠时朝向相同的方向。这些骰子堆叠，偏移和电耦合。在一个实施例中，堆叠的骰子具有诸如SDRAM装置的缓冲功能，并且被包括在具有附加管芯的多芯片封装（MCP）中，该芯片包括通道功能和其上的控制器功能。骰子被封装在单个包装中以放置在印刷电路板上用于诸如盘驱动器的存储装置中。

2. 发明申请

US20120192724A1 GRILL INSERTS AND TOOL FOR THE SAME 有权
标题翻译： GRILL插件和工具
公开(公告)号：US20120192724A1
公开(公告)日：2012-08-02
申请号：US13362936
申请日：2012-01-31
申请人： Ryan T. Harrison , Thomas Parel , Robert Warren , Kenneth M. Brazell , Zachary Scott , Scott Kippes , Mark Huggins , Taku Ohi , Jason Porter Whitmire , Adam Clark , Robert McCracken , Christopher Clearman
发明人： Ryan T. Harrison , Thomas Parel , Robert Warren , Kenneth M. Brazell , Zachary Scott , Scott Kippes , Mark Huggins , Taku Ohi , Jason Porter Whitmire , Adam Clark , Robert McCracken , Christopher Clearman
IPC分类号： A47J36/16 , B66C1/42
CPC分类号： A47J37/067 , A47J37/0786 , A47J45/10
摘要： A tool for removing an interchangeable cooking insert from a grill has a handle end and an engagement end. A handle extends from the handle end toward the engagement end. A support arm extends from the handle toward the engagement end. The support arm has a first lateral edge defining a first lifting hook and a second lateral edge defining a second lifting hook. The first lifting hook and second lifting hook are configured to engage a portion of the cooking insert. A support pin extends across the support arm between the first lateral edge and the second lateral edge. A latch member is pivotally coupled to one of the support arm and the handle. The latch member includes a first end selectively engageable with a portion of the cooking insert and a second end extending through the handle for actuation of the latching member by a user.
摘要翻译：用于从烤架移除可互换烹饪插入件的工具具有手柄端和接合端。手柄从手柄端向接合端延伸。支撑臂从手柄向接合端延伸。支撑臂具有限定第一提升钩的第一侧边缘和限定第二提升钩的第二侧边缘。第一提升钩和第二提升钩构造成接合烹饪插入件的一部分。支撑销在第一侧边缘和第二侧边缘之间延伸穿过支撑臂。闩锁构件枢转地联接到支撑臂和手柄中的一个。闩锁构件包括可选择性地与烹饪插入件的一部分接合的第一端和延伸穿过手柄的第二端，用于由使用者致动闩锁构件。

3. 发明授权

US07685482B2 Tap sampling at double rate 有权
标题翻译：以双倍速率抽样
公开(公告)号：US07685482B2
公开(公告)日：2010-03-23
申请号：US11015749
申请日：2004-12-17
申请人： Robert Warren
发明人： Robert Warren
IPC分类号： G01R31/28 , G01R31/26 , G11C29/00
CPC分类号： G01R31/318555 , G01R31/318536 , G01R31/318552 , G01R31/318558 , G01R31/318563 , G01R31/3187
摘要： An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge.
摘要翻译：一种集成电路，包括：用于接收测试数据的至少一个测试输入; 所述至少一个测试输入和要测试的电路之间的测试控制电路; 其中测试数据在上升时钟沿和下降时钟沿被计时。

4. 发明申请

US20070215897A1 GaAs integrated circuit device and method of attaching same 有权
标题翻译： GaAs集成电路器件及其连接方法
公开(公告)号：US20070215897A1
公开(公告)日：2007-09-20
申请号：US11377690
申请日：2006-03-16
申请人： Hong Shen , Ravi Ramanathan , Qiuliang Luo , Robert Warren , Usama Abdali
发明人： Hong Shen , Ravi Ramanathan , Qiuliang Luo , Robert Warren , Usama Abdali
IPC分类号： H01L33/00
CPC分类号： H01L23/4924 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/32 , H01L24/83 , H01L2224/04026 , H01L2224/05599 , H01L2224/32225 , H01L2224/83801 , H01L2924/00014 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/05042 , H01L2924/10157 , H01L2924/10329 , H01L2924/14 , H01L2924/01031
摘要： A gallium arsenide (GaAs) integrated circuit device is provided. The GaAs circuit device has a GaAs substrate with a copper contact layer for making electrical ground contact with a pad of a target device. Although copper is known to detrimentally affect GaAS devices, the copper contact layer is isolated from the GaAs substrate using a barrier layer. The barrier layer may be, for example, a layer of nickel vanadium (NiV). This nickel vanadium (NiV) barrier protects the gallium arsenide substrate from the diffusion effects of the copper contact layer. An organic solder preservative may coat the exposed copper to reduce oxidation effects. In some cases, a gold or copper seed layer may be deposited on the GaAs substrate prior to depositing the copper contact layer.
摘要翻译：提供了一种砷化镓（GaAs）集成电路器件。 GaAs电路器件具有带有铜接触层的GaAs衬底，用于与目标器件的焊盘进行电接地接触。虽然已知铜不利地影响GaAS器件，但铜接触层使用阻挡层与GaAs衬底隔离。阻挡层可以是例如镍钒（NiV）层。该镍钒（NiV）屏障保护砷化镓衬底免受铜接触层的扩散作用。有机锡防腐剂可以涂覆暴露的铜以减少氧化效应。在一些情况下，在沉积铜接触层之前，可以在GaAs衬底上沉积金或铜种子层。

5. 发明申请

US20060211233A1 Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure 审中-公开
标题翻译：用于制造具有通过用于外部封装连接和相关结构的晶片通孔的晶片级封装的方法
公开(公告)号：US20060211233A1
公开(公告)日：2006-09-21
申请号：US11085968
申请日：2005-03-21
申请人： Qing Gan , Anthony Lobianco , Robert Warren
发明人： Qing Gan , Anthony Lobianco , Robert Warren
IPC分类号： H01L21/44
CPC分类号： B81C1/00301 , B81B2207/095 , H01L23/10 , H01L23/3114 , H01L2924/0002 , H01L2924/01079 , H01L2924/00
摘要： According to an exemplary embodiment, a method for fabricating a wafer level package includes forming a polymer layer on a device wafer, where the device wafer includes at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The method further includes bonding a protective wafer to the device wafer. The method further includes forming at least one via in the protective wafer, where the at least one via extends through the protective wafer and is situated over the at least one device wafer contact pad. The method further includes forming at least one protective wafer contact pad on the protective wafer, where the at least one protective wafer contact pad is situated over the at least one via and electrically connected to the at least one device wafer contact pad.
摘要翻译：根据示例性实施例，用于制造晶片级封装的方法包括在器件晶片上形成聚合物层，其中器件晶片包括至少一个器件晶片接触焊盘和器件，并且其中至少一个器件晶片接触焊盘电连接到设备。该方法还包括将保护晶片接合到器件晶片。该方法还包括在保护晶片中形成至少一个通孔，其中至少一个通孔延伸穿过保护晶片并且位于至少一个器件晶片接触焊盘上方。所述方法还包括在所述保护晶片上形成至少一个保护性晶片接触焊盘，其中所述至少一个保护性晶片接触焊盘位于所述至少一个通孔上并电连接至所述至少一个器件晶片接触焊盘。

6. 发明申请

US20060031728A1 Method and apparatus for measuring digital timing paths by setting a scan mode of sequential storage elements 有权
标题翻译：通过设置顺序存储元件的扫描模式来测量数字定时路径的方法和装置
公开(公告)号：US20060031728A1
公开(公告)日：2006-02-09
申请号：US10912375
申请日：2004-08-05
申请人： Robert Warren , Paul Huelskamp , Bradley MacMonagle
发明人： Robert Warren , Paul Huelskamp , Bradley MacMonagle
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/31858
摘要： A method and apparatus are provided for performing on-board, in-circuit, and/or wafer level scan-based testing of integrated circuits. With the apparatus and method, one or more sequential storage elements, e.g., flip/flops, are coupled to combinational logic and are configured to have an additional port for receiving a scan mode signal. The scan mode signal sets the sequential storage element into one of two modes of operation: static mode in which the sequential storage element's output does not change on a falling edge of a scan enable signal or a transitional mode in which the sequential storage element's output is permitted to change on the falling edge. With sequential storage elements configured in this manner, a configuration scan is performed to set certain ones of the sequential storage elements into a static mode and other sequential storage elements into a transitional mode. A test pattern is then applied to the sequential storage elements and a pattern capture cycle is commenced.
摘要翻译：提供了一种用于执行集成电路的板上，在线和/或晶片级扫描的测试的方法和装置。利用该装置和方法，一个或多个顺序存储元件，例如触发器耦合到组合逻辑，并被配置为具有用于接收扫描模式信号的附加端口。扫描模式信号将顺序存储元件设置为两种操作模式之一：静态模式，其中顺序存储元件的输出在扫描使能信号的下降沿或在顺序存储元件的输出为允许在下降沿改变。利用以这种方式配置的顺序存储元件，执行配置扫描以将顺序存储元件中的某些顺序存储元件设置为静态模式，将其他顺序存储元件设置为过渡模式。然后将测试图案应用于顺序存储元件，并且开始模式捕获周期。

7. 发明申请

US20060010657A1 Specialized strap system 审中-公开
标题翻译：专业表带系统
公开(公告)号：US20060010657A1
公开(公告)日：2006-01-19
申请号：US11107135
申请日：2005-04-14
申请人： Robert Warren , Ryan Matzinger
发明人： Robert Warren , Ryan Matzinger
IPC分类号： A44B21/00
CPC分类号： A45F3/14 , G10G5/005 , Y10T24/13
摘要： The present invention provides an advantageous strap system for use with various objects, such as musical instruments, tools, or other objects that can be carried or supported using a neck strap. In an example embodiment of the present invention, a strap system is provided which comprises a fabric neck loop having two ends and a first connection component affixed to at least one end of the neck loop. A connection strap comprising a length of fabric is provided. A second connection component is affixed to a first end of the connection strap for enabling a connection with the first connection component. A connection means may be affixed to a second end of the connection strap for enabling a connection between an object and the connection strap. The connection means may comprise a hook, a snap ring, or the like.
摘要翻译：本发明提供了一种有利的带系统，用于各种物体，例如乐器，工具或可使用颈带携带或支撑的其它物体。在本发明的示例性实施例中，提供了一种带系统，其包括具有两个端部的织物颈环和固定到颈环的至少一端的第一连接部件。提供包括一定长度的织物的连接带。第二连接部件固定在连接带的第一端上，以实现与第一连接部件的连接。连接装置可以固定到连接带的第二端，以使物体和连接带之间的连接能够实现。连接装置可以包括钩，卡环等。

8. 发明申请

US20050289368A1 Power management device and method 有权
标题翻译：电源管理装置及方法
公开(公告)号：US20050289368A1
公开(公告)日：2005-12-29
申请号：US10881270
申请日：2004-06-29
申请人： Lai Kein Chang , Lucas Lee , Kian Ooi , Brian Nollinger Nollinger , Robert Warren
发明人： Lai Kein Chang , Lucas Lee , Kian Ooi , Brian Nollinger Nollinger , Robert Warren
IPC分类号： G06F1/28 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3268 , Y02D10/154
摘要： A power management circuit is provided for a data storage device that is adapted for communicating with a host via an interface circuit. The power management circuit is responsive to a utilization of a control circuit of the data storage device, determined independently of the communication between the data storage device and the host, in providing a supply power to the data storage device. A method is provided comprising connecting a data storage device with a host via an interface circuit; sending data transfer commands from the host to the interface circuit; and monitoring the utilization of a control circuit of the data storage device in terms of the rate at which commands are processed by the control circuit for use in selectively providing a supply power to the data storage device.
摘要翻译：为适用于经由接口电路与主机进行通信的数据存储装置提供电源管理电路。功率管理电路响应于数据存储设备的控制电路的利用，其独立于数据存储设备和主机之间的通信而确定，以向数据存储设备提供电源。提供了一种通过接口电路将数据存储设备与主机连接的方法; 从主机向接口电路发送数据传输命令; 并且根据用于选择性地向数据存储装置提供电源的控制电路处理命令的速率来监视数据存储装置的控制电路的利用率。

9. 发明申请

US20050283696A1 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US20050283696A1
公开(公告)日：2005-12-22
申请号：US11101167
申请日：2005-04-07
申请人： Robert Warren , Robert Mills
发明人： Robert Warren , Robert Mills
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/00
CPC分类号： G01R31/318552
摘要： An integrated circuit including functional circuitry; test circuitry connected to the functional circuitry, wherein the test circuitry is arranged to control the testing of the functional circuitry; and clock signal generating circuitry connected to both the functional circuitry and the test circuitry. The test circuitry is arranged to use the clock signal for testing the functional circuitry.
摘要翻译：包括功能电路的集成电路; 连接到所述功能电路的测试电路，其中所述测试电路被布置成控制所述功能电路的测试; 以及连接到功能电路和测试电路两者的时钟信号发生电路。测试电路被设置为使用时钟信号来测试功能电路。

10. 发明申请

US20050216802A1 TAP time division multiplexing with scan test 有权
标题翻译： TAP时分复用与扫描测试
公开(公告)号：US20050216802A1
公开(公告)日：2005-09-29
申请号：US11015772
申请日：2004-12-17
申请人： Robert Warren
发明人： Robert Warren
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318563 , G01R31/318536
摘要： An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.
摘要翻译：一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

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