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1. 发明授权

US06569606B1 Method of reducing photoresist shadowing during angled implants 失效
标题翻译：在倾斜植入物期间减少光致抗蚀剂遮蔽的方法
公开(公告)号：US06569606B1
公开(公告)日：2003-05-27
申请号：US09626666
申请日：2000-07-27
申请人： David Donggang Wu , William R. Roche , Massud Aminpur , Scott D. Luning , Karen L. E. Turnqest
发明人： David Donggang Wu , William R. Roche , Massud Aminpur , Scott D. Luning , Karen L. E. Turnqest
IPC分类号： G03C500
CPC分类号： H01L29/66492 , G03F7/2002 , H01L21/0274 , H01L21/26586
摘要： The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a structure above a semiconducting substrate, forming a layer of photoresist above the structure and the substrate, and positioning the substrate in an exposure tool that has a light source and a focal plane. The method further comprises positioning the surface of the layer of photoresist in an exposure plane that is different from the focal plane of the exposure tool, exposing the photoresist to the light source of the exposure tool while the surface of the photoresist is in the exposure plane, and developing the layer of photoresist to define an opening in the layer of photoresist around the structure on the substrate.
摘要翻译：本发明涉及一种在半导体器件中形成晕轮植入物的方法。在一个说明性实施例中，该方法包括在半导体衬底上形成结构，在结构和衬底之上形成光致抗蚀剂层，并将衬底定位在具有光源和焦平面的曝光工具中。该方法还包括将光致抗蚀剂层的表面定位在与曝光工具的焦平面不同的曝光平面中，将光致抗蚀剂暴露于曝光工具的光源，同时光致抗蚀剂的表面处于曝光平面并且显影所述光致抗蚀剂层以在所述衬底上的所述结构周围的光致抗蚀剂层中限定开口。

2. 发明授权

US07087509B1 Method of forming a gate electrode on a semiconductor device and a device incorporating same 有权
标题翻译：在半导体器件上形成栅电极的方法和结合其的器件
公开(公告)号：US07087509B1
公开(公告)日：2006-08-08
申请号：US09676197
申请日：2000-09-28
申请人： William R. Roche , David Donggang Wu , Massud Aminpur , Scott D. Luning
发明人： William R. Roche , David Donggang Wu , Massud Aminpur , Scott D. Luning
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28035 , H01L21/28114 , H01L29/42376 , H01L29/4916
摘要： The present invention is directed to a semiconductor device having a gate electrode includes of a plurality of sidewalls, each having a recess formed therein. The present invention is also directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of dopant material in a layer of polysilicon and etching the layer of polysilicon to define a gate electrode having a plurality of sidewalls, each of which have a recess formed therein.
摘要翻译：本发明涉及一种半导体器件，其具有包括多个侧壁的栅电极，每个侧壁均形成有凹部。本发明还涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括在多晶硅层中形成掺杂剂材料层并蚀刻多晶硅层以限定具有多个侧壁的栅电极，每个侧壁在其中形成有凹陷。

3. 发明授权

US06624035B1 Method of forming a hard mask for halo implants 有权
标题翻译：形成光晕植入物的硬掩模的方法
公开(公告)号：US06624035B1
公开(公告)日：2003-09-23
申请号：US09523631
申请日：2000-03-13
申请人： Scott D. Luning , David Donggang Wu , Massud Aminpur
发明人： Scott D. Luning , David Donggang Wu , Massud Aminpur
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586
摘要： The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a surface of a semiconducting substrate, and forming a hard mask layer above the gate electrode and the substrate. The method further comprises patterning the hard mask layer to define an opening in the hard mask layer, and performing an angled implantation process through the opening in the hard mask to introduce dopant atoms into the substrate under at least a portion of the gate electrode.
摘要翻译：本发明涉及一种在半导体器件中形成晕轮植入物的方法。在一个说明性实施例中，该方法包括在半导体衬底的表面上方形成栅电极，以及在栅电极和衬底上形成硬掩模层。该方法还包括图案化硬掩模层以在硬掩模层中限定开口，以及通过硬掩模中的开口进行成角度的注入工艺，以在栅电极的至少一部分下将掺杂剂原子引入衬底中。

4. 发明授权

US06727558B1 Channel isolation using dielectric isolation structures 有权
标题翻译：使用介质隔离结构的通道隔离
公开(公告)号：US06727558B1
公开(公告)日：2004-04-27
申请号：US09784790
申请日：2001-02-15
申请人： Michael P. Duane , David D. Wu , Massud Aminpur , Scott D. Luning
发明人： Michael P. Duane , David D. Wu , Massud Aminpur , Scott D. Luning
IPC分类号： H01L21425
CPC分类号： H01L29/0847 , H01L21/28123 , H01L21/823412 , H01L21/823481 , H01L29/1079 , H01L29/51 , H01L29/518 , H01L29/665 , H01L29/6659
摘要： A method is provided, the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.
摘要翻译：提供了一种方法，该方法包括在衬底层上形成栅极电介质，以及在栅极电介质上方形成栅极导体。该方法还包括在邻近栅极电介质的衬底中形成至少一个电介质隔离结构。

5. 发明授权

US06617219B1 Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors 有权
标题翻译：用于通过修改高速微处理器的源极/漏极延伸来降低铣刀电容的半导体器件和方法
公开(公告)号：US06617219B1
公开(公告)日：2003-09-09
申请号：US09784628
申请日：2001-02-15
申请人： Michael P. Duane , David D. Wu , Massud Aminpur , Scott D. Luning
发明人： Michael P. Duane , David D. Wu , Massud Aminpur , Scott D. Luning
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/1041 , H01L29/6659 , H01L29/7833
摘要： A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.
摘要翻译：提供了一种方法，所述方法包括在衬底的表面上形成栅极电介质，在栅极电介质上方形成导电栅极结构，所述导电栅极结构具有边缘区域，并且形成与所述栅极电介质邻近的源极/漏极延伸（SDE）导电栅结构。该方法还包括在导电栅极结构的边缘区域下方的衬底中形成掺杂剂贫化SDE区域。

6. 发明授权

US07763547B2 Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics 有权
标题翻译：在低k层间电介质形成通孔和沟槽期间增强工艺灵活性的技术
公开(公告)号：US07763547B2
公开(公告)日：2010-07-27
申请号：US11199526
申请日：2005-08-08
申请人： Thomas Werner , Matthias Schaller , Massud Aminpur
发明人： Thomas Werner , Matthias Schaller , Massud Aminpur
IPC分类号： H01L21/3065 , H01L21/302
CPC分类号： H01L21/31138 , H01L21/31116 , H01L21/76808 , H01L21/76834
摘要： In an etch process for forming via openings and trench openings in a low-k dielectric layer, the material removal of an underlying etch stop layer is decoupled from the etching through the low-k dielectric in that the reduction in thickness is substantially achieved during the resist removal. For this purpose, the resist plasma etch may correspondingly be controlled to obtain the desired target thickness of the etch stop layer, wherein fluorine may be provided from an external source and/or fluorine may be generated in a controlled manner from polymer layers deposited within the etch chamber.
摘要翻译：在用于在低k电介质层中形成通孔开口和沟槽开口的蚀刻工艺中，下层蚀刻停止层的材料去除与通过低k电介质的蚀刻分离，因为厚度的减小在抵抗力消除。为此，可以相应地控制抗蚀剂等离子体蚀刻以获得蚀刻停止层的期望目标厚度，其中可以从外部源提供氟，和/或氟可以以受控的方式从沉积在蚀刻室。

7. 发明授权

US06482726B1 Control trimming of hard mask for sub-100 nanometer transistor gate 有权
标题翻译：对100纳米晶体管栅极的硬掩模进行控制修整
公开(公告)号：US06482726B1
公开(公告)日：2002-11-19
申请号：US09690152
申请日：2000-10-17
申请人： Massud Aminpur , David Wu , Scott Luning
发明人： Massud Aminpur , David Wu , Scott Luning
IPC分类号： H01L213205
CPC分类号： H01L21/28123 , H01L29/6659
摘要： A method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. The method also includes forming a trimmed photoresist mask above the second hard mask layer, and forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension. The method further includes forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension, and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.
摘要翻译：提供了一种方法，该方法包括在衬底层上方形成栅介质层，在栅极介电层上方形成栅极导体层，在栅极导体层之上形成第一硬掩模层，并形成第二硬掩模层第一硬掩模层。该方法还包括在第二硬掩模层之上形成修整的光致抗蚀剂掩模，并且在第二硬掩模层中使用经修剪的光致抗蚀剂掩模形成图案化的硬掩模以去除第二硬掩模层的部分，图案化硬掩模具有第一尺寸。该方法还包括通过去除与图案化的硬掩模相邻的第一硬掩模层的部分来形成第一硬掩模层中的选择性蚀刻的硬掩模，该选择性蚀刻的硬掩模具有小于第一尺寸的第二尺寸，以及形成栅极结构，其使用选择性蚀刻的硬掩模以去除栅极介电层上方的栅极导体层的部分。

8. 发明授权

US07314793B2 Technique for controlling mechanical stress in a channel region by spacer removal 有权
标题翻译：通过间隔物去除来控制通道区域的机械应力的技术
公开(公告)号：US07314793B2
公开(公告)日：2008-01-01
申请号：US11047129
申请日：2005-01-31
申请人： Kai Frohberg , Matthias Schaller , Massud Aminpur , Martin Mazur , Roberto Klingler
发明人： Kai Frohberg , Matthias Schaller , Massud Aminpur , Martin Mazur , Roberto Klingler
IPC分类号： H01L21/8238
CPC分类号： H01L29/6653 , H01L21/3215 , H01L21/32155 , H01L21/823807 , H01L21/823864 , H01L29/4966 , H01L29/665 , H01L29/7843 , Y10S438/938
摘要： During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.
摘要翻译：在形成晶体管元件期间，在离子注入和硅化之后去除侧壁间隔物或至少部分地回蚀，从而使接触蚀刻停止层与潜在的漏极和源极区域的机械耦合更有效。因此，机械应力可以基本上由接触蚀刻步骤层引起，而不是间隔元件和蚀刻停止层的组合，从而显着地促进了沟道区域中的应力工程。通过额外进行等离子体处理，可以在不同的晶体管器件中产生不同量的应力，而不会不利地导致工艺复杂性。

9. 发明授权

US07151055B2 Technique for forming a gate electrode by using a hard mask 失效
标题翻译：通过使用硬掩模形成栅电极的技术
公开(公告)号：US07151055B2
公开(公告)日：2006-12-19
申请号：US10974119
申请日：2004-10-27
申请人： Massud Aminpur , Kay Hellig
发明人： Massud Aminpur , Kay Hellig
IPC分类号： H01L21/4763
CPC分类号： H01L29/66553 , H01L21/28123 , H01L29/78
摘要： The anisotropic etch process for forming circuit elements such as a gate electrode is accomplished by using a hard mask instead of a resist feature, thereby avoiding a complex resist trim process when critical dimensions are required, which are well below the resolution of the involved photolithography. Moreover, the critical dimension may be adjusted by means of a deposition process rather than by a resist trim process.
摘要翻译：用于形成诸如栅电极的电路元件的各向异性蚀刻工艺通过使用硬掩模而不是抗蚀剂特征来实现，从而在需要临界尺寸时避免复杂的抗蚀剂修整过程，这远远低于所涉及的光刻的分辨率。此外，临界尺寸可以通过沉积工艺而不是通过抗蚀剂修整工艺来调节。

10. 发明申请

US20060172525A1 Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics 有权
标题翻译：在低k层间电介质形成通孔和沟槽期间增强工艺灵活性的技术
公开(公告)号：US20060172525A1
公开(公告)日：2006-08-03
申请号：US11199526
申请日：2005-08-08
申请人： Thomas Werner , Matthias Schaller , Massud Aminpur
发明人： Thomas Werner , Matthias Schaller , Massud Aminpur
IPC分类号： H01L21/467
CPC分类号： H01L21/31138 , H01L21/31116 , H01L21/76808 , H01L21/76834
摘要： In an etch process for forming via openings and trench openings in a low-k dielectric layer, the material removal of an underlying etch stop layer is decoupled from the etching through the low-k dielectric in that the reduction in thickness is substantially achieved during the resist removal. For this purpose, the resist plasma etch may correspondingly be controlled to obtain the desired target thickness of the etch stop layer, wherein fluorine may be provided from an external source and/or fluorine may be generated in a controlled manner from polymer layers deposited within the etch chamber.
摘要翻译：在用于在低k电介质层中形成通孔开口和沟槽开口的蚀刻工艺中，下层蚀刻停止层的材料去除与通过低k电介质的蚀刻分离，因为厚度的减小在抵抗力消除。为此，可以相应地控制抗蚀剂等离子体蚀刻以获得蚀刻停止层的期望目标厚度，其中可以从外部源提供氟，和/或氟可以以受控的方式从沉积在蚀刻室。

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