专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6128706A Apparatus and method for a load bias--load with intent to semaphore 失效
标题翻译：用于信号量的负载偏置负载的装置和方法
公开(公告)号：US6128706A
公开(公告)日：2000-10-03
申请号：US018165
申请日：1998-02-03
申请人： William R. Bryg , Stephen G. Burger , Gary N. Hammond , Michael L. Ziegler
发明人： William R. Bryg , Stephen G. Burger , Gary N. Hammond , Michael L. Ziegler
IPC分类号： G06F9/312 , G06F13/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087
摘要： Apparatus and method for efficiently sharing data in support of hardware he coherency and coordinated in software with semaphore instructions. Accordingly, a new instruction called "Load-Bias" which, in addition to normal load operations, requests a private copy of the data, and hints to the hardware cache to try to maintain ownership until the next memory reference from that processor. When used with the Cmpxchg instruction semaphore operation, the Load-Bias instruction will reduce coherency traffic, and minimize the possibility of coherency ping-ponging or system deadlock that causes the condition in which no processor is getting useful work done.
摘要翻译：用于有效地共享数据以支持硬件高速缓存一致性并利用信号量指令在软件中协调的装置和方法。因此，称为“负载偏置”的新指令除了正常的加载操作之外，还请求数据的私有副本，并向硬件缓存提示，以尝试维持所有权，直到来自该处理器的下一个存储器引用。当与Cmpxchg指令信号量操作一起使用时，负载偏移指令将减少一致性流量，并最大限度地减少一致性乒乓或系统死锁的可能性，从而导致无处理器无法正常工作的条件。

2. 发明授权

US06199144B1 Method and apparatus for transferring data in a computer system 失效
标题翻译：用于在计算机系统中传送数据的方法和装置
公开(公告)号：US06199144B1
公开(公告)日：2001-03-06
申请号：US09001336
申请日：1997-12-31
申请人： Judge K. Arora , William R. Bryg , Stephen G. Burger , Gary N. Hammond , Michael L. Ziegler
发明人： Judge K. Arora , William R. Bryg , Stephen G. Burger , Gary N. Hammond , Michael L. Ziegler
IPC分类号： G06F1200
CPC分类号： G06F12/0833
摘要： A method and apparatus for transferring data from a first memory location to a second memory location in a computer system. A load instruction is executed, and, in response, data is transferred from a first memory location to a second memory location during a single bus transaction. During the same bus transaction, a request is made to invalidate a copy of the data that is stored in a third memory location if the load instruction indicates to do so.
摘要翻译：一种用于将数据从计算机系统中的第一存储器位置传送到第二存储器位置的方法和装置。执行加载指令，并且作为响应，在单个总线事务期间，数据从第一存储器位置传送到第二存储器位置。在相同的总线事务期间，如果加载指令指示这样做，则请求使存储在第三存储器位置的数据的副本无效。

3. 发明授权

US06393544B1 Method and apparatus for calculating a page table index from a virtual address 有权
公开(公告)号：US06393544B1
公开(公告)日：2002-05-21
申请号：US09430793
申请日：1999-10-31
申请人： William R. Bryg , Stephen G. Burger , Gary N. Hammond , James O. Hays , Jerome C. Huck , Jonathan K. Ross , Sunil Saxena , Koichi Yamada
发明人： William R. Bryg , Stephen G. Burger , Gary N. Hammond , James O. Hays , Jerome C. Huck , Jonathan K. Ross , Sunil Saxena , Koichi Yamada
IPC分类号： G06F1200
CPC分类号： G06F12/1018 , G06F2212/652
摘要： A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single “long format” page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2K bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2L bytes long. Next, a mask is formed based on the size of the page table. A first address portion is then formed using the base address of the page table and the mask, and a second address portion is formed using the table offset and the mask. Finally, the entry address is formed by combining the first and second address portions. By providing a single algorithm capable of generating a page table entry for both long and short format page tables, the present invention reduces the amount of logic required to access both page table formats, without significantly affecting execution speed.

4. 发明授权

US06216214B1 Apparatus and method for a virtual hashed page table 失效
标题翻译：虚拟散列页表的装置和方法
公开(公告)号：US06216214B1
公开(公告)日：2001-04-10
申请号：US09018326
申请日：1998-02-03
申请人： William R. Bryg , Stephen G. Burger , James O. Hays , John M. Kessenich , Jonathan K. Ross , Gary N. Hammond , Sunil Saxena , Koichi Yamada
发明人： William R. Bryg , Stephen G. Burger , James O. Hays , John M. Kessenich , Jonathan K. Ross , Gary N. Hammond , Sunil Saxena , Koichi Yamada
IPC分类号： G06F1210
CPC分类号： G06F12/1036 , G06F2212/681
摘要： The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.
摘要翻译：本发明一般涉及利用虚拟存储器管理系统中的单个地址空间或多个地址空间模型有效地翻译虚拟地址的装置和方法。特别地，虚拟哈希页表（VHPT）是翻译后备缓冲区（TLB）层次结构的扩展，旨在增强虚拟地址转换性能。虚拟哈希页表（VHPT）有效地支持用于将虚拟地址转换为物理地址的两种操作系统的不同方法。这直接有利于地址解析高度经常的路径。

5. 发明授权

US06430670B1 Apparatus and method for a virtual hashed page table 失效
标题翻译：虚拟散列页表的装置和方法
公开(公告)号：US06430670B1
公开(公告)日：2002-08-06
申请号：US09703536
申请日：2000-11-01
申请人： William R. Bryg , Stephen G. Burger , James O. Hays , John M. Kessenich , Jonathan K. Ross , Gary N. Hammond , Sunil Saxena , Koichi Yamada
发明人： William R. Bryg , Stephen G. Burger , James O. Hays , John M. Kessenich , Jonathan K. Ross , Gary N. Hammond , Sunil Saxena , Koichi Yamada
IPC分类号： G06F1200
CPC分类号： G06F12/1036 , G06F2212/681
摘要： The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.
摘要翻译：本发明一般涉及利用虚拟存储器管理系统中的单个地址空间或多个地址空间模型有效地翻译虚拟地址的装置和方法。特别地，虚拟哈希页表（VHPT）是翻译后备缓冲区（TLB）层次结构的扩展，旨在增强虚拟地址转换性能。虚拟哈希页表（VHPT）有效地支持用于将虚拟地址转换为物理地址的两种操作系统的不同方法。这直接有利于地址解析高度经常的路径。

6. 发明授权

US06408373B2 Method and apparatus for pre-validating regions in a virtual addressing scheme 失效
标题翻译：用于在虚拟寻址方案中预先验证区域的方法和装置
公开(公告)号：US06408373B2
公开(公告)日：2002-06-18
申请号：US09850878
申请日：2001-05-07
申请人： Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg , Rajiv Gupta , Gary N. Hammond , Koichi Yamada
发明人： Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg , Rajiv Gupta , Gary N. Hammond , Koichi Yamada
IPC分类号： G06F1200
CPC分类号： G06F12/1036
摘要： A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time. When a virtual-to-physical entry is established for a page in a region having an RID stored in a region register, the RID and VRN are stored in the appropriate fields of the TLB entry. In addition, the valid field is set and the rpV field is set to indicate that the TLB entry contains an active VRN-to-RID mapping, thereby pre-validating the region. When a physical address is translated into a virtual address, a VRN and a VPN are extracted from the virtual address and provided to the TLB. The TLB is searched to find an entry having a set valid field, a set rpV field, and VRN and VPN fields containing entries matching the VRN and VPN extracted from the virtual address. If such an entry is found, the protection and access attributes field is used to determine whether the requested access is allowed. If the requested access is allowed, the PPN from the PPN field of the TLB entry is combined with an offset from the virtual address to produce a physical address that is used to complete the memory access.
摘要翻译：一种方法和装置通过将虚拟区域号（VRN）位和区域标识符（RID）存储在翻译后备缓冲器（TLB）条目中来对虚拟寻址方案中的区域进行预验证。通过将VRN位和RID都存储在TLB表中，可以在执行大多数TLB访问时旁路区域寄存器，从而去除区域寄存器中TLB查找过程的关键路径并提高系统性能。根据本发明的TLB包括具有有效字段，区域预验证有效（rpV）字段，虚拟区域号（VRN）字段，虚拟页号（VPN）字段），区域标识符（RID）字段，保护和访问属性字段以及物理页号（PPN）字段。此外，一组区域寄存器包含在任何给定时间处于活动状态的RID。当在具有存储在区域寄存器中的RID的区域中的页面建立虚拟到物理条目时，RID和VRN被存储在TLB条目的相应字段中。另外，设置有效字段，并且设置rpV字段以指示TLB条目包含活动的VRN到RID映射，从而预先验证该区域。当物理地址被转换为虚拟地址时，从虚拟地址提取VRN和VPN，并提供给TLB。搜索TLB以找到具有设置的有效字段，集合rpV字段的条目，以及包含与从虚拟地址提取的VRN和VPN匹配的条目的VRN和VPN字段。如果找到这样的条目，则使用保护和访问属性字段来确定所请求的访问是否被允许。如果允许所请求的访问，则来自TLB条目的PPN字段的PPN与来自虚拟地址的偏移组合，以产生用于完成存储器访问的物理地址。

7. 发明授权

US5940872A Software and hardware-managed translation lookaside buffer 失效
标题翻译：软件和硬件管理的翻译后备缓冲区
公开(公告)号：US5940872A
公开(公告)日：1999-08-17
申请号：US742467
申请日：1996-11-01
申请人： Gary N. Hammond , Koichi Yamada , Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg
发明人： Gary N. Hammond , Koichi Yamada , Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg
IPC分类号： G06F12/10 , G11C12/10
CPC分类号： G06F12/1027
摘要： A translation lookaside buffer (TLB) is provided including a first storage location in the TLB for storing at least a portion of a first virtual to physical memory translation. The first storage location in the TLB is both hardware-managed and software-managed. The TLB also includes a second storage location in the TLB for storing at least a portion of a second virtual to physical memory translation. The second storage location in the TLB is only software-managed.
摘要翻译：提供了翻译后备缓冲器（TLB），包括TLB中的第一存储位置，用于存储第一虚拟到物理存储器转换的至少一部分。 TLB中的第一个存储位置是硬件管理和软件管理的。 TLB还包括TLB中的第二存储位置，用于存储第二虚拟到物理存储器转换的至少一部分。 TLB中的第二个存储位置只能由软件管理。

8. 发明授权

US5535352A Access hints for input/output address translation mechanisms 失效
标题翻译：访问输入/输出地址转换机制的提示
公开(公告)号：US5535352A
公开(公告)日：1996-07-09
申请号：US217587
申请日：1994-03-24
申请人： K. Monroe Bridges , Robert Brooks , William R. Bryg , Stephen G. Burger , Eric W. Hamilton , Helen Nusbaum , Brendan A. Voge , Michael L. Ziegler
发明人： K. Monroe Bridges , Robert Brooks , William R. Bryg , Stephen G. Burger , Eric W. Hamilton , Helen Nusbaum , Brendan A. Voge , Michael L. Ziegler
IPC分类号： G06F12/08 , G06F12/02 , G06F12/10 , G06F13/28 , G06F13/00
CPC分类号： G06F13/28 , G06F12/1081
摘要： A computing system includes a main memory and an input/output adapter. The input/output adapter accesses a translation map. The translation map maps input/output page numbers to memory address page numbers. Entries to the translation map are generated so that each entry includes an address of a data page in the main memory and transaction configuration information. The transaction configuration information is utilized by the input/output adapter during data transactions to and from the data page.
摘要翻译：计算系统包括主存储器和输入/输出适配器。输入/输出适配器访问翻译图。翻译地图将输入/输出页码映射到内存地址页码。生成到翻译图的条目，使得每个条目包括主存储器中的数据页的地址和事务配置信息。事务配置信息由输入/输出适配器在与数据页之间的数据事务期间被利用。

9. 发明授权

US5515522A Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache 失效
标题翻译：由位于处理器外部的输入/输出适配器使用的相干索引生成，用于检测更新的数据版本是否驻留在缓存内
公开(公告)号：US5515522A
公开(公告)日：1996-05-07
申请号：US201433
申请日：1994-02-24
申请人： K. Monroe Bridges , William R. Bryg , Stephen G. Burger , James M. Hull , Michael L. Ziegler
发明人： K. Monroe Bridges , William R. Bryg , Stephen G. Burger , James M. Hull , Michael L. Ziegler
IPC分类号： G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/0835
摘要： A computing system includes a memory bus, a main memory, an I/O adapter and a processor. The main memory, the I/O adapter and the processor are connected to the bus. The I/O adapter includes a translation map. The translation map maps I/O page numbers to memory address page numbers. The translation map includes coherence indices. The processor includes a cache and an instruction execution means. The instruction execution means generates coherence indices to be stored in the translation map. The instruction execution means performs in hardware a hash operation to generate the coherence indices.
摘要翻译：计算系统包括存储器总线，主存储器，I / O适配器和处理器。主存储器，I / O适配器和处理器连接到总线。 I / O适配器包括翻译图。翻译地图将I / O页码映射到内存地址页码。翻译地图包括一致性指标。处理器包括缓存和指令执行装置。指令执行装置生成要存储在转换图中的一致性索引。指令执行装置在硬件中执行散列操作以产生相干指数。

10. 发明授权

US5784708A Translation mechanism for input/output addresses 失效
标题翻译：输入/输出地址的翻译机制
公开(公告)号：US5784708A
公开(公告)日：1998-07-21
申请号：US647074
申请日：1996-05-08
申请人： K. Monroe Bridges , Robert Brooks , William R. Bryg , Stephen G. Burger , Michael L. Ziegler
发明人： K. Monroe Bridges , Robert Brooks , William R. Bryg , Stephen G. Burger , Michael L. Ziegler
IPC分类号： G06F13/12 , G06F12/02 , G06F12/10
CPC分类号： G06F12/1081 , G06F12/1027 , G06F2212/206
摘要： A computing system includes a memory bus, an input/output bus, a main memory, and an input/output adapter. The memory bus provides information transfer. The input/output bus also provides information transfer. For example the input/output bus is an input/output bus onto which is connected input/output devices. The main memory is connected to the memory bus. The main memory includes a page directory. The page directory stores translations. Each translation in the page directory includes a portion of an address for data transferred over the input/output bus, for example, the page address portion of I/O bus address. Each translation in the page directory also is indexed by a portion of an address for a memory location within the main memory, for example, the page address portion of the address for the memory location. The input/output adapter is connected to the memory bus and the input/output bus. The input/output adapter includes an input/output translation look-aside buffer. The input/output translation look-aside buffer includes a portion of the translations stored in the page directory.
摘要翻译：计算系统包括存储器总线，输入/输出总线，主存储器和输入/输出适配器。内存总线提供信息传输。输入/输出总线还提供信息传输。例如，输入/输出总线是输入/输出总线，连接有输入/输出总线。主存储器连接到存储器总线。主内存包括一个页面目录。页面目录存储翻译。页面目录中的每个翻译包括通过输入/输出总线传送的数据的地址的一部分，例如I / O总线地址的页面地址部分。页面目录中的每个翻译也由主存储器内的存储器位置的地址的一部分索引，例如存储器位置的地址的页面地址部分。输入/输出适配器连接到存储器总线和输入/输出总线。输入/输出适配器包括一个输入/输出转换后备缓冲器。输入/输出转换后备缓冲器包括存储在页目录中的一部分翻译。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式