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    • 7. 发明申请
    • LITHOGRAPHY FOR PITCH REDUCTION
    • 缩小地图
    • US20100028801A1
    • 2010-02-04
    • US12184438
    • 2008-08-01
    • Steven J. HolmesXuefeng HuaWillard E. Conley
    • Steven J. HolmesXuefeng HuaWillard E. Conley
    • G03F7/20
    • H01L21/0337H01L21/0338
    • In one embodiment, a photoresist is lithographically patterned to form an array of patterned photoresist portions having a pitch near twice a minimum feature size. Fluorine-containing polymer spacers are formed on sidewalls of the patterned photoresist portions. The pattern of the fluorine-containing polymer spacers is transferred into an underlying layer to form a pattern having a sublithographic pitch. In another embodiment, a first pattern in a first photoresist is transferred into a first ARC layer underneath to form first ARC portions. A planarizing second optically dense layer, a second ARC layer, and a second photoresist are applied over the first ARC portions. A second pattern in the second photoresist is transferred into the second ARC layer to form second ARC portions. The combination of the first ARC portions and second ARC portions function as an etch mask to pattern an underlying layer with a composite pattern having a sublithographic pitch.
    • 在一个实施例中,光刻胶被图案化以形成具有接近两倍最小特征尺寸的间距的图案化光刻胶部分的阵列。 含氟聚合物间隔物形成在图案化的光致抗蚀剂部分的侧壁上。 将含氟聚合物间隔物的图案转移到下层中以形成具有亚光刻间距的图案。 在另一个实施例中,将第一光致抗蚀剂中的第一图案转移到下面的第一ARC层中以形成第一ARC部分。 在第一ARC部分上施加平坦化的第二光致密层,第二ARC层和第二光致抗蚀剂。 将第二光致抗蚀剂中的第二图案转移到第二ARC层中以形成第二ARC部分。 第一ARC部分和第二ARC部分的组合用作蚀刻掩模,以用具有亚光刻间距的复合图案对下面的层进行图案化。
    • 9. 发明申请
    • INTEGRATED CIRCUIT WITH DEGRADATION MONITORING
    • 集成电路与降解监测
    • US20140132315A1
    • 2014-05-15
    • US13677800
    • 2012-11-15
    • Puneet SharmaMatthew A. ThompsonWillard E. Conley
    • Puneet SharmaMatthew A. ThompsonWillard E. Conley
    • H03L7/00
    • G01R31/3016G01R31/2884
    • An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
    • 一种包括劣化监测电路的集成电路。 劣化监视电路包括具有延迟元件的比较电路,该延迟元件包括耦合到定时路径的数据节点的输入,并具有输出以提供数据节点的数据信号的延迟信号。 比较电路包括逻辑比较器,其提供数据节点的数据信号和延迟元件的输出之间的逻辑比较。 监视电路包括采样电路,该采样电路提供对于时钟信号线的时钟信号采样的逻辑比较器的输出的采样信号。 监视电路包括保持电路,该保持电路提供指示在时钟信号线的时钟信号的边沿转换的预定时间内数据节点的数据信号的信号。
    • 10. 发明授权
    • Method of making a semiconductor device using negative photoresist
    • 使用负性光致抗蚀剂制造半导体器件的方法
    • US08119334B2
    • 2012-02-21
    • US12112058
    • 2008-04-30
    • Willard E. Conley
    • Willard E. Conley
    • G03F7/26
    • H01L21/31144G03F7/091H01L21/76802
    • Negative photoresist over an insulating layer is exposed to radiation according to a pattern for an opening in the insulating layer for filling conductive material. A post of the negative photoresist is left over the location where the opening in the insulating layer is to be formed. A developable hard mask is formed over the post by a spin-on process so that the hard mask over the post is much thinner than directly over the insulating layer. An etch back is performed to remove the hard mask from over the post so that the post of negative photoresist is thus exposed. The post is removed to form an opening in the hard mask. An etch is performed to form the opening in the insulating layer aligned to the opening in the hard mask. The opening in the insulating layer is filled with the conductive material.
    • 根据用于填充导电材料的绝缘层中的开口的图案将绝缘层上的负光致抗蚀剂暴露于辐射。 负光致抗蚀剂的柱留在要形成绝缘层中的开口的位置。 通过旋涂工艺在柱上形成可显影的硬掩模,使得柱上的硬掩模比直接在绝缘层上方薄得多。 执行回蚀以从柱上移除硬掩模,使得负光致抗蚀剂的柱由此暴露。 去除柱子以形成硬掩模中的开口。 执行蚀刻以在与硬掩模中的开口对准的绝缘层中形成开口。 绝缘层中的开口填充有导电材料。