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1. 发明申请

US20110287630A1 Methods of Processing Semiconductor Substrates In Forming Scribe Line Alignment Marks 有权
标题翻译：在形成划线对准标记中处理半导体衬底的方法
公开(公告)号：US20110287630A1
公开(公告)日：2011-11-24
申请号：US13196524
申请日：2011-08-02
申请人： William R. Brown , David Kewley , Adam Olson
发明人： William R. Brown , David Kewley , Adam Olson
IPC分类号： H01L21/308 , H01L21/302
CPC分类号： H01L21/308 , G03F9/708 , G03F9/7084 , H01L21/0337 , H01L21/3086
摘要： A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features. Individual of the photoresist blocks have an opposing pair of second pattern edges in the cross-section that self-align laterally outward of the first pattern edges to the laterally innermost sidewalls of the features during the patterning.
摘要翻译：在形成划线对准标记中处理半导体衬底的方法包括在半导体衬底的划线区域内形成间距倍数非电路特征。在横截面中，特征的个体具有小于在光刻图案化基底中使用的最小光刻特征尺寸的最大宽度。光刻胶沉积在特征上。将其图案化以形成在横截面中单独地接收在相应的一对特征之间的光致抗蚀剂块。各对的特征的个体在横截面中具有横向最内侧的侧壁。光致抗蚀剂块的个体在横截面中具有相对的一对第一图案边缘，其横向相对于相应的一对特征的横向最内侧的侧壁向内间隔开。光致抗蚀剂块的个体在横截面中具有相对的一对第二图案边缘，其在图案化期间自动对准第一图案边缘的横向外侧到特征的侧向最内侧。

2. 发明授权

US08003482B2 Methods of processing semiconductor substrates in forming scribe line alignment marks 有权
标题翻译：在形成划线对准标记时处理半导体衬底的方法
公开(公告)号：US08003482B2
公开(公告)日：2011-08-23
申请号：US12622171
申请日：2009-11-19
申请人： William R. Brown , David Kewley , Adam Olson
发明人： William R. Brown , David Kewley , Adam Olson
IPC分类号： H01L21/302
CPC分类号： H01L21/308 , G03F9/708 , G03F9/7084 , H01L21/0337 , H01L21/3086
摘要： A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features. Individual of the photoresist blocks have an opposing pair of second pattern edges in the cross-section that self-align laterally outward of the first pattern edges to the laterally innermost sidewalls of the features during the patterning.
摘要翻译：在形成划线对准标记中处理半导体衬底的方法包括在半导体衬底的划线区域内形成间距倍数非电路特征。在横截面中，特征的个体具有小于在光刻图案化基底中使用的最小光刻特征尺寸的最大宽度。光刻胶沉积在特征上。将其图案化以形成在横截面中单独地接收在相应的一对特征之间的光致抗蚀剂块。各对的特征的个体在横截面中具有横向最内侧的侧壁。光致抗蚀剂块的个体在横截面中具有相对的一对第一图案边缘，其横向相对于相应的一对特征的横向最内侧的侧壁向内间隔开。光致抗蚀剂块的个体在横截面中具有相对的一对第二图案边缘，其在图案化期间自动对准第一图案边缘的横向外侧到特征的侧向最内侧。

3. 发明申请

US20110117719A1 METHODS OF PROCESSING SEMICONDUCTOR SUBSTRATES IN FORMING SCRIBE LINE ALIGNMENT MARKS 有权
标题翻译：在形成筛选线对齐标记中加工半导体基板的方法
公开(公告)号：US20110117719A1
公开(公告)日：2011-05-19
申请号：US12622171
申请日：2009-11-19
申请人： William R. Brown , David Kewley , Adam Olson
发明人： William R. Brown , David Kewley , Adam Olson
IPC分类号： H01L21/306
CPC分类号： H01L21/308 , G03F9/708 , G03F9/7084 , H01L21/0337 , H01L21/3086
摘要： A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features. Individual of the photoresist blocks have an opposing pair of second pattern edges in the cross-section that self-align laterally outward of the first pattern edges to the laterally innermost sidewalls of the features during the patterning.
摘要翻译：在形成划线对准标记中处理半导体衬底的方法包括在半导体衬底的划线区域内形成间距倍数非电路特征。在横截面中，特征的个体具有小于在光刻图案化基底中使用的最小光刻特征尺寸的最大宽度。光刻胶沉积在特征上。将其图案化以形成在横截面中单独地接收在相应的一对特征之间的光致抗蚀剂块。各对的特征的个体在横截面中具有横向最内侧的侧壁。光致抗蚀剂块的个体在横截面中具有相对的一对第一图案边缘，其横向相对于相应的一对特征的横向最内侧的侧壁向内间隔开。光致抗蚀剂块的个体在横截面中具有相对的一对第二图案边缘，其在图案化期间自动对准第一图案边缘的横向外侧到特征的侧向最内侧。

4. 发明申请

US20130052566A1 LITHOGRAPHY METHODS, METHODS FOR FORMING PATTERNING TOOLS AND PATTERNING TOOLS 有权
标题翻译：图形方法，形成图案工具和绘图工具的方法
公开(公告)号：US20130052566A1
公开(公告)日：2013-02-28
申请号：US13214865
申请日：2011-08-22
申请人： Jianming Zhou , Scott L. Light , David Kewley , Prasanna Srinivasan , Anton deVilliers
发明人： Jianming Zhou , Scott L. Light , David Kewley , Prasanna Srinivasan , Anton deVilliers
IPC分类号： G03F7/20 , G03F1/14
CPC分类号： G03F7/20 , G03F1/26 , G03F1/32 , G03F7/70433 , G03F7/70883
摘要： Methods of lithography, methods for forming patterning tools, and patterning tools are described. One such patterning tool include an active region that forms a first diffraction image on a lens when in use, and an inactive region that forms a second diffraction image on a lens when in use. The inactive region includes a pattern of phase shifting features formed in a substantially transparent material of the patterning tool. Patterning tools and methods, as described, can be used to compensate for lens distortion from effects such as localized heating.
摘要翻译：描述了光刻方法，用于形成图案形成工具的方法和图案形成工具。一种这样的图案形成工具包括在使用时在透镜上形成第一衍射图像的有源区域和在使用时在透镜上形成第二衍射图像的非活性区域。非活性区域包括形成在图案形成工具的基本上透明的材料中的相移特征的图案。如所描述的图案化工具和方法可用于补偿透镜失真，例如局部加热等影响。

5. 发明授权

US08334211B2 Process for improving critical dimension uniformity of integrated circuit arrays 有权
标题翻译：提高集成电路阵列临界尺寸均匀性的工艺
公开(公告)号：US08334211B2
公开(公告)日：2012-12-18
申请号：US12360738
申请日：2009-01-27
申请人： David Kewley
发明人： David Kewley
IPC分类号： H01L21/308
CPC分类号： H01L27/0207 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/2815 , H01L29/06
摘要： Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.
摘要翻译：公开了采用附加掩模工艺来集成电路（IC）器件阵列图案化以改进中心到边缘CD均匀性的方法。在一个实施例中，在衬底的第一区域上的掩模层中形成特征的重复图案。然后，在屏蔽层中的特征上施加阻挡掩模。阻挡掩模被配置为将第一区域的阵列区域与第一区域的周边区域区分开。随后，将阵列区域中的特征图案转移到衬底中。在该实施例中，由于掩模层中的中心/边缘没有区别，因此可以将蚀刻剂均匀地引入掩模层。因此，可以在随后定义的阵列中实现CD均匀性。

6. 发明授权

US08609302B2 Lithography methods, methods for forming patterning tools and patterning tools 有权
公开(公告)号：US08609302B2
公开(公告)日：2013-12-17
申请号：US13214865
申请日：2011-08-22
申请人： Jianming Zhou , Scott L. Light , David Kewley , Prasanna Srinivasan , Anton deVilliers
发明人： Jianming Zhou , Scott L. Light , David Kewley , Prasanna Srinivasan , Anton deVilliers
IPC分类号： G03F1/60
CPC分类号： G03F7/20 , G03F1/26 , G03F1/32 , G03F7/70433 , G03F7/70883
摘要： Methods of lithography, methods for forming patterning tools, and patterning tools are described. One such patterning tool include an active region that forms a first diffraction image on a lens when in use, and an inactive region that forms a second diffraction image on a lens when in use. The inactive region includes a pattern of phase shifting features formed in a substantially transparent material of the patterning tool. Patterning tools and methods, as described, can be used to compensate for lens distortion from effects such as localized heating.

7. 发明申请

US20090130852A1 PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS 有权
标题翻译：改进集成电路阵列关键尺寸均匀性的方法
公开(公告)号：US20090130852A1
公开(公告)日：2009-05-21
申请号：US12360738
申请日：2009-01-27
申请人： David Kewley
发明人： David Kewley
IPC分类号： H01L21/3065
CPC分类号： H01L27/0207 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/2815 , H01L29/06
摘要： Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.
摘要翻译：公开了采用附加掩模工艺来集成电路（IC）器件阵列图案化以改善中心到边缘CD均匀性的方法。在一个实施例中，在衬底的第一区域上的掩模层中形成特征的重复图案。然后，在屏蔽层中的特征上施加阻挡掩模。阻挡掩模被配置为将第一区域的阵列区域与第一区域的周边区域区分开。随后，将阵列区域中的特征图案转移到衬底中。在该实施例中，由于掩模层中的中心/边缘没有区别，因此可以将蚀刻剂均匀地引入掩模层。因此，可以在随后定义的阵列中实现CD均匀性。

8. 发明授权

US07488685B2 Process for improving critical dimension uniformity of integrated circuit arrays 有权
标题翻译：提高集成电路阵列临界尺寸均匀性的工艺
公开(公告)号：US07488685B2
公开(公告)日：2009-02-10
申请号：US11411401
申请日：2006-04-25
申请人： David Kewley
发明人： David Kewley
IPC分类号： H01L21/302
CPC分类号： H01L27/0207 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/2815 , H01L29/06
摘要： Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.
摘要翻译：公开了采用附加掩模工艺来集成电路（IC）器件阵列图案化以改进中心到边缘CD均匀性的方法。在一个实施例中，在衬底的第一区域上的掩模层中形成特征的重复图案。然后，在屏蔽层中的特征上施加阻挡掩模。阻挡掩模被配置为将第一区域的阵列区域与第一区域的周边区域区分开。随后，将阵列区域中的特征图案转移到衬底中。在该实施例中，由于掩模层中的中心/边缘没有区别，因此可以将蚀刻剂均匀地引入掩模层。因此，可以在随后定义的阵列中实现CD均匀性。

9. 发明申请

US20070249170A1 Process for improving critical dimension uniformity of integrated circuit arrays 有权
标题翻译：提高集成电路阵列临界尺寸均匀性的工艺
公开(公告)号：US20070249170A1
公开(公告)日：2007-10-25
申请号：US11411401
申请日：2006-04-25
申请人： David Kewley
发明人： David Kewley
IPC分类号： H01L21/302 , H01L21/461 , H01L29/04
CPC分类号： H01L27/0207 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/2815 , H01L29/06
摘要： Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.
摘要翻译：公开了采用附加掩模工艺来集成电路（IC）器件阵列图案化以改善中心到边缘CD均匀性的方法。在一个实施例中，在衬底的第一区域上的掩模层中形成特征的重复图案。然后，在屏蔽层中的特征上施加阻挡掩模。阻挡掩模被配置为将第一区域的阵列区域与第一区域的周边区域区分开。随后，将阵列区域中的特征图案转移到衬底中。在该实施例中，由于掩模层中的中心/边缘没有区别，所以可以将蚀刻剂均匀地引入掩模层。因此，可以在随后定义的阵列中实现CD均匀性。

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