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1. 发明申请

US20130301671A1 Detecting Thermal Interface Material ('TIM') Between A Heat Sink And An Integrated Circuit 有权
标题翻译：检测散热片和集成电路之间的热界面材料（'TIM'）
公开(公告)号：US20130301671A1
公开(公告)日：2013-11-14
申请号：US13469286
申请日：2012-05-11
申请人： William M. Megarity , LUKE D. REMIS , GREGORY D. SELLMAN
发明人： William M. Megarity , LUKE D. REMIS , GREGORY D. SELLMAN
IPC分类号： G01N25/18
CPC分类号： G01N25/18
摘要： Detecting TIM between a heat sink and an integrated circuit, the integrated circuit including TIM detection points adapted to receive TIM upon installation of the heat sink and including a TIM detection device configured to be activated upon contact with TIM, including: receiving, upon installation of the heat sink on the integrated circuit and the TIM, TIM in one or more of the TIM detection points; activating, by the TIM in each of the one or more TIM detection points receiving the TIM, a TIM detection device; determining, by a TIM detection module of the integrated circuit in dependence upon the activations of the TIM detection devices, sufficiency of the TIM; and responsive to determining that the TIM between the heat sink and the integrated circuit is insufficient, controlling, in real-time by the TIM detection module, operation of the integrated circuit to reduce heat generated by the integrated circuit.
摘要翻译：在散热器和集成电路之间检测TIM，所述集成电路包括适于在安装所述散热器时接收TIM的TIM检测点，并且包括配置为在与所述TIM接触时被激活的TIM检测装置，包括：在安装集成电路上的散热片和TIM，TIM在一个或多个TIM检测点; 通过TIM接收TIM接收到的一个或多个TIM检测点中的每一个来激活TIM检测装置; 根据TIM检测装置的激活，通过集成电路的TIM检测模块确定TIM的充分性; 并且响应于确定散热器和集成电路之间的TIM不足，通过TIM检测模块实时控制集成电路的操作以减少由集成电路产生的热量。

2. 发明申请

US20130304954A1 Dynamically Optimizing Bus Frequency Of An Inter-Integrated Circuit ('I2C') Bus 有权
标题翻译：动态优化集成电路（I2C）总线的总线频率
公开(公告)号：US20130304954A1
公开(公告)日：2013-11-14
申请号：US13467332
申请日：2012-05-09
申请人： MICHAEL DECESARIS , STEVEN C. JACOBSON , LUKE D. REMIS , GREGORY D. SELLMAN
发明人： MICHAEL DECESARIS , STEVEN C. JACOBSON , LUKE D. REMIS , GREGORY D. SELLMAN
IPC分类号： G06F13/00
CPC分类号： G06F1/324 , G06F9/44 , G06F13/38 , G06F13/4282
摘要： Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.
摘要翻译：优化I2C总线频率，总线包括耦合主节点和从节点的信号线，耦合到上升时间检测电路的信号线监视信号线的电压，电压在逻辑低电平和逻辑高电平之间交替，其中优化频率包括：在信号线上升期间检测第一电压，第一电压大于逻辑低电压; 启动一个计数器，为电路的每个时钟周期增加一次; 检测信号线上的第二电压，第二电压大于第一电压并小于逻辑高电平; 停止柜台根据时钟周期和计数器值计算上升时间; 确定上升时间是否大于最大阈值; 并且如果计算的上升时间大于最大阈值，则增加I2C总线频率。

3. 发明申请

US20130346763A1 Increasing Data Transmission Rate In An Inter-Integrated Circuit ('I2C') System 有权
标题翻译：在内部集成电路（“I2C”）系统中增加数据传输速率
公开(公告)号：US20130346763A1
公开(公告)日：2013-12-26
申请号：US13530473
申请日：2012-06-22
申请人： MICHAEL DECESARIS , LUKE D. REMIS , GREGORY D. SELLMAN
发明人： MICHAEL DECESARIS , LUKE D. REMIS , GREGORY D. SELLMAN
IPC分类号： G06F1/26 , G06F1/04
CPC分类号： G06F13/4291 , G06F2213/0016
摘要： Increasing data transmission rate in an I2C system that includes an I2C source device and an destination device, the source device coupled to the destination device through an SDL and SCL, including: receiving in parallel, by the destination device, an SDL data signal and an SCL data signal, the SCL data signal encoded with bits; and, for each bit of the SCL data signal: detecting rise time of the bit and determining, in dependence upon the detected rise time, whether the bit represents a first binary value or a second binary value including: determining that the bit represents a first binary value when the detected rise time is less than a predefined threshold; and determining that the bit represents a second binary value when the detected rise time is not less than the predefined threshold.
摘要翻译：包括I2C源设备和目标设备的I2C系统中的数据传输速率提高，源设备通过SDL和SCL耦合到目标设备，包括：由目标设备并行接收SDL数据信号和 SCL数据信号，SCL数据信号用位编码; 并且对于SCL数据信号的每一位：检测位的上升时间，并且根据检测到的上升时间确定该位是否表示第一二进制值或第二二进制值，包括：确定该位表示第一个当检测到的上升时间小于预定阈值时，二进制值; 以及当所检测的上升时间不小于所述预定阈值时，确定所述比特表示第二二进制值。

4. 发明申请

US20130275636A1 ACCESSING PERIPHERAL DEVICES 有权
标题翻译：访问外围设备
公开(公告)号：US20130275636A1
公开(公告)日：2013-10-17
申请号：US13445235
申请日：2012-04-12
申请人： MICHAEL DECESARIS , LUKE D. REMIS , GREGORY D. SELLMAN , STEVEN L. VANDERLINDEN
发明人： MICHAEL DECESARIS , LUKE D. REMIS , GREGORY D. SELLMAN , STEVEN L. VANDERLINDEN
IPC分类号： G06F13/42
CPC分类号： G06F13/4291
摘要： A hardware system comprises a master device and a slave device that are coupled by a signal line. A frequency generator in the master device places a selected frequency signal on the signal line. A frequency detector/comparator in the slave device, which is coupled to the signal line, determines whether the selected frequency signal on the signal line matches a predetermined frequency for the slave device. If the selected frequency signal matches the predetermined frequency, then a chip select node on the slave device is enabled, in order to permit a data exchange session between the master device and the slave device.
摘要翻译：硬件系统包括通过信号线耦合的主设备和从设备。主设备中的频率发生器将选定的频率信号放置在信号线上。耦合到信号线的从设备中的频率检测器/比较器确定信号线上选定的频率信号是否与从设备的预定频率相匹配。如果所选择的频率信号与预定频率匹配，则从设备上的片选选择节点被使能，以便允许主设备和从设备之间的数据交换会话。

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