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    • 1. 发明授权
    • Mechanism for coalescing non-cacheable stores
    • 合并不可缓存商店的机制
    • US06078587A
    • 2000-06-20
    • US880469
    • 1997-06-23
    • William L. LynchMichael G. Lavelle
    • William L. LynchMichael G. Lavelle
    • G09G5/36H04L12/28H04L12/56
    • G09G5/363
    • Data is collected from multiple data packets for group transfer on a data path so as to maximize utilization of the data path. A particularly suitable data path is one that is coupled to transfer data to a graphics frame buffer. In collecting data from multiple data packets, data from individual packets are designated for loading onto the data path. In specific embodiments, data from a packet will be designated for loading onto the data path only if it is determined that the data is noncacheable data, the data would not overwrite other valid designated but not yet loaded data, or the resulting data to be transferred as a group would target data locations within a permissible locus of data locations, such as a contiguous range of addresses. The designated data are loaded onto the data path as a group for actual transfer. In a specific embodiment, there is a mask associated with each data packet that indicates which portions of each packet's possible data actually contain data to be transferred. In a specific embodiment, there is also a mask associated with each group transfer of data that indicates which portions of possible data in a group transfer actually contain data to be transferred.
    • 数据从多个数据包收集,用于在数据路径上进行组传输,以便最大限度地利用数据路径。 特别合适的数据路径是耦合到将数据传送到图形帧缓冲器的数据路径。 在从多个数据分组收集数据时,指定来自各个分组的数据用于加载到数据路径上。 在具体实施例中,仅当确定数据是不可缓存的数据时,数据将不会覆盖其他有效的指定但尚未加载的数据或所得到的要传送的数据 作为一组将针对诸如连续地址范围的数据位置的容许轨迹内的数据位置。 指定的数据作为实际传送的组加载到数据路径上。 在具体实施例中,存在与每个数据分组相关联的掩码,其指示每个分组的可能数据的哪些部分实际包含要传送的数据。 在具体实施例中,还存在与数据的每组传输相关联的掩码,其指示组传输中的可能数据的哪些部分实际上包含要传送的数据。
    • 4. 发明授权
    • System and method for adaptively balancing network traffic over router output ports
    • 用于自适应地平衡路由器输出端口上的网络流量的系统和方法
    • US07554914B1
    • 2009-06-30
    • US10396192
    • 2003-03-24
    • Anthony J. LiWilliam L. Lynch
    • Anthony J. LiWilliam L. Lynch
    • H04L12/56
    • H04L47/10H04L45/745H04L47/125H04L47/30H04L49/254
    • A method and system for determining an output port upon which to transmit a packet in a router having a plurality of output ports adapted to be coupled with an adjacent router. In one embodiment, a list is created of output ports that are coupled with the adjacent router, and the list is modified based on network traffic. A port is selected from the list of ports, and the packet is transmitted over the selected port. In one example, the list is modified continuously as a background process based on network traffic. The list may be modified by determining a port which is under-utilized, determining a port which is over-utilized, and substituting in the list one or more instances of the port which is over-utilized with one or more instances of the port which is under-utilized. In this manner, a router can adaptively and evenly distribute the packet transmission traffic over the output ports.
    • 一种用于确定在具有适于与相邻路由器耦合的多个输出端口的路由器中传送分组的输出端口的方法和系统。 在一个实施例中,创建与相邻路由器耦合的输出端口的列表,并且基于网络流量修改列表。 从端口列表中选择端口,并通过所选端口传输数据包。 在一个示例中,该列表作为基于网络流量的后台进程被连续地修改。 可以通过确定未充分利用的端口,确定被过度利用的端口,并且在列表中替换与该端口的一个或多个实例过度利用的端口的一个或多个实例来修改该列表, 没有充分利用。 以这种方式,路由器可以在输出端口上自适应均匀地分配分组传输流量。
    • 8. 发明授权
    • Non-inclusive cache system using pipelined snoop bus
    • 使用流水线监听总线的非包容性缓存系统
    • US6076147A
    • 2000-06-13
    • US881745
    • 1997-06-24
    • William L. LynchAl Yamauchi
    • William L. LynchAl Yamauchi
    • G06F12/08
    • G06F12/0831G06F12/0811
    • A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data which is absent from the external cache. A pipelined snoop bus is ported to each of the set of tags of the plurality of on-chip caches and transmits a snoop address to the plurality of on-chip caches. A system interface unit is responsive to a received snoop request to scan the external cache and to apply the snoop address of the snoop request to the pipelined snoop bus. A plurality of response signal lines respectively extend from the plurality of on-chip caches to the system interface unit, each of the signal lines for transmitting a snoop response from a corresponding one of the on-board caches to the system interface unit. The set of tags can be implemented by dual-porting the cache tags, or by providing a duplicate and dedicated set of snoop tags.
    • 非包容性缓存系统包括外部高速缓存和多个片上高速缓存,每个具有与之相关联的一组标签,片上高速缓存中的至少一个包括外部高速缓存中不存在的数据。 流水线窥探总线被移植到多个片上高速缓存中的每组标签中,并将一个窥探地址发送到多个片上高速缓存。 系统接口单元响应于所接收的窥探请求来扫描外部高速缓存并将窥探请求的窥探地址应用于流水线窥探总线。 多个响应信号线分别从多个片上高速缓存延伸到系统接口单元,每个信号线用于从相应的板载高速缓存发送窥探响应到系统接口单元。 标签集可以通过双端口缓存标签来实现,或者通过提供一组重复的和专用的snoop标签集来实现。