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1. 发明授权

US4803622A Programmable I/O sequencer for use in an I/O processor 失效
标题翻译：用于I / O处理器的可编程I / O定序器
公开(公告)号：US4803622A
公开(公告)日：1989-02-07
申请号：US46633
申请日：1987-05-07
申请人： William L. Bain, Jr. , Robert C. Bedichek , George W. Cox , Gerhard Grassl , Craig B. Peterson , Justin R. Rattner , Gurbir Singh , Gurbir Singh , John L. Wipfli
发明人： William L. Bain, Jr. , Robert C. Bedichek , George W. Cox , Gerhard Grassl , Craig B. Peterson , Justin R. Rattner , Gurbir Singh , Gurbir Singh , John L. Wipfli
IPC分类号： G06F13/14 , G06F13/12 , G06F13/38 , G06F3/00
CPC分类号： G06F13/124
摘要： An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers. The PLA decodes an ACCESS instruction to start an operation by loading the first register set descriptor, and then decodes sequential SUPPLY instructions to the entry. Each SUPPLY instruction loads an empty register set descriptor field to be used when the current register set descriptor field is exhausted.
摘要翻译：一种用于在执行单元（EU-10），寄存器文件（14）和连接到总线（28）的设备之间提供数据路径的I / O总线定序器。可编程逻辑阵列（PLA-18）存储控制服务表（20）的程序。服务表包括分成字段的多个条目。解码后的其中一个字段指示PLA对总线音序器执行什么样的操作。连接到I / O请求线（30）和服务表（20）的线路选择（优先级）逻辑（22）确定PLA要使用的服务表条目。连接到I / O总线端口（26）和PLA（18）的总线接口在I / O总线端口（26）和寄存器文件（14）之间路由数据，其条目通过使用寄存器套。服务表字段包括用于存储寄存器组缓冲器的状态的寄存器集描述符。 PLA通过加载第一个寄存器集描述符对ACCESS指令进行解码以开始操作，然后将顺序的SUPPLY指令解码到该条目。每个SUPPLY指令加载当前寄存器集描述符字段耗尽时要使用的空寄存器集描述符字段。

2. 发明授权

US4829425A Memory-based interagent communication mechanism 失效
标题翻译：基于内存的代理间通信机制
公开(公告)号：US4829425A
公开(公告)日：1989-05-09
申请号：US168635
申请日：1988-03-01
申请人： William L. Bain, Jr. , David G. Carson , George W. Cox , Robert C. Duzett , Brad W. Hosler , Scott A. Ogilvie , Craig B. Peterson , John L. Wipfli
发明人： William L. Bain, Jr. , David G. Carson , George W. Cox , Robert C. Duzett , Brad W. Hosler , Scott A. Ogilvie , Craig B. Peterson , John L. Wipfli
IPC分类号： G06F13/40
CPC分类号： G06F13/404
摘要： An I/O processor for controlling data transfer between a local bus and an I/O bus. An Execution Unit, an I/O bus sequencer, and a local bus sequencer are connected to a register file. The register file is uniformly addressed and each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer have read/write access to the register file. The register file is comprised of a plurality of register sets. The Execution Unit includes a programmed processor which is programmed to allocate the register sets among tasks running on the processor by passing register-set descriptors between the tasks in the form of messages. The local bus sequencer includes a packet-oriented multiprocessor bus, there being a variable number of bytes in each of the packets. The I/O sequencer includes logic for multibyte sequencing of data at a bus-dependent data rate between the I/O bus and the register file. Each of the tasks includes a task frame, each task frame including register-set pointers. The register-set pointers map between logical addresses used in the instructions of the tasks used to access the pointers and physical register-set addresses used to access the register. Programmed logic in each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer dynamically allocate the register sets to the sending and destination tasks.
摘要翻译：用于控制本地总线和I / O总线之间的数据传输的I / O处理器。执行单元，I / O总线排序器和本地总线顺控程序连接到寄存器文件。寄存器文件被均匀地寻址，执行单元，本地总线排序器和I / O总线排序器中的每一个具有对寄存器文件的读/写访问。寄存器文件由多个寄存器组构成。执行单元包括编程处理器，其被编程为通过在消息形式的任务之间传递寄存器集描述符来在处理器上运行的任务之间分配寄存器集。本地总线定序器包括面向分组的多处理器总线，每个分组中存在可变数量的字节。 I / O定序器包括用于在I / O总线和寄存器文件之间以总线相关数据速率对数据进行多字节排序的逻辑。每个任务包括任务帧，每个任务帧包括寄存器集指针。寄存器集指针映射在用于访问指针的任务的指令中使用的逻辑地址和用于访问寄存器的物理寄存器集地址之间。每个执行单元，本地总线排序器和I / O总线顺控程序中的程序逻辑动态地将寄存器组分配给发送和目标任务。

3. 发明授权

US4853849A Multi-tasking register set mapping system which changes a register set pointer block bit during access instruction 失效
标题翻译：多任务寄存器集映射系统，在访问指令期间改变寄存器集指针块位
公开(公告)号：US4853849A
公开(公告)日：1989-08-01
申请号：US942608
申请日：1986-12-17
申请人： William L. Bain, Jr. , Marcos de Oliveira Camargo , Robert C. Duzett , Artur H. Lederhofer , Craig B. Peterson , John L. Wipfli
发明人： William L. Bain, Jr. , Marcos de Oliveira Camargo , Robert C. Duzett , Artur H. Lederhofer , Craig B. Peterson , John L. Wipfli
IPC分类号： G06F9/46 , G06F9/48 , G06F13/12
CPC分类号： G06F13/124 , G06F13/126
摘要： An I/O processor includes an execution unit (EU), a register file, an I/O bus sequencer and a local bus sequencer. The EU decodes an ACCESS instruction having a pointer to a parameter register comprised of: a number of fields for storing a sequencer code identifying one of the sequencers; a logical byte specifying a location in memory to be addressed and valid and block bits; a reply register set pointer to a register set in the register file designated to receive a reply to the ACCESS instruction; and, a length field specifying the location and length of a data block in the register file from which data is to be obtained. A data pointer is generated by taking the logical byte in the parameter register and passing it through a register set mapper to produce a register file physical address. The valid bit of the logical byte is turned off as it is translated by the register the mapper so that the bus sequencer can take control over the corresponding register set. The block bit is set upon the condition that the ACCESS instruction attempts to access a register set whose valid bit is not set, and the block bit is reset upon the condition that the task which is executing the ACCESS instruction attempts to access a register set whose block and valid bits are set.
摘要翻译： I / O处理器包括执行单元（EU），寄存器文件，I / O总线排序器和本地总线排序器。 EU解码具有指向参数寄存器的指针的ACCESS指令，该指令包括：用于存储识别其中一个定序器的定序器代码的多个字段; 指定存储器中要被寻址和有效的位置的逻辑字节和块位; 回复寄存器设置指向寄存器文件中设置的寄存器文件的指针，用于接收对ACCESS指令的回复; 以及指定要从其获得数据的寄存器文件中的数据块的位置和长度的长度字段。通过取参数寄存器中的逻辑字节并通过寄存器集映射器产生寄存器文件物理地址来生成数据指针。逻辑字节的有效位被关闭，因为它由寄存器转换为映射器，以便总线排序器可以控制相应的寄存器集。在ACCESS指令尝试访问其有效位未设置的寄存器组的情况下，块位被置位，并且在执行ACCESS指令的任务试图访问其寄存器组的条件下，块位被复位块和有效位被置位。

4. 发明授权

US5959606A Rasterizer for pattern generator 失效
标题翻译：图案发生器光栅
公开(公告)号：US5959606A
公开(公告)日：1999-09-28
申请号：US327581
申请日：1994-10-24
申请人： Allan L. Goodman , Morris H. Green , Matthew J. Jolley , Robin L. Teitzel , John L. Wipfli
发明人： Allan L. Goodman , Morris H. Green , Matthew J. Jolley , Robin L. Teitzel , John L. Wipfli
IPC分类号： G11C11/401 , G03F1/00 , G06F17/50 , G09G5/393 , G09G5/399 , G09G5/36
CPC分类号： G03F1/00 , G09G5/393
摘要： A rasterizer, particularly suited for generating patterns for semiconductor masks and the like is described. An 8.times.8 array uses RAS, CAS and WE signals in addition to the memory address for accessing the array. A state machine is used to convert the pattern data (e.g., type of object orientation, etc.) into accessing data with the WE generator being driven through a ROM.
摘要翻译：描述了特别适用于生成半导体掩模等的图案的光栅化器。 8x8阵列除了用于访问阵列的存储器地址之外还使用RAS，CAS和WE信号。使用状态机将图形数据（例如，对象方向的类型等）转换为通过ROM驱动WE生成器的访问数据。

5. 发明授权

US4806921A Rasterizer for pattern generator 失效
标题翻译：图案发生器光栅
公开(公告)号：US4806921A
公开(公告)日：1989-02-21
申请号：US784856
申请日：1985-10-04
申请人： Allan L. Goodman , Morris H. Green , Matthew J. Jolley , Robin L. Teitzel , John L. Wipfli
发明人： Allan L. Goodman , Morris H. Green , Matthew J. Jolley , Robin L. Teitzel , John L. Wipfli
IPC分类号： G11C11/401 , G03F1/00 , G06F17/50 , G09G5/393 , G09G5/399 , G09G1/16
CPC分类号： G03F1/00 , G09G5/393
摘要： A rasterizer, particularly suited for generating patterns for semiconductor masks and the like is described. An 8.times.8 array uses RAS, CAS and WE signals in addition to the memory address for accessing the array. A state machine is used to convert the pattern data (e.g., type of object orientation, etc.) into accessing data with the WE generator being driven through a ROM.
摘要翻译：描述了特别适用于生成半导体掩模等的图案的光栅化器。 8x8阵列除了用于访问阵列的存储器地址之外还使用RAS，CAS和WE信号。使用状态机将图形数据（例如，对象方向的类型等）转换为通过ROM驱动WE生成器的访问数据。

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