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1. 发明授权

US07512826B2 Method, apparatus, and product for an efficient virtualized time base in a scaleable multi-processor computer 失效
标题翻译：用于可扩展多处理器计算机中高效虚拟化时基的方法，设备和产品
公开(公告)号：US07512826B2
公开(公告)日：2009-03-31
申请号：US11110180
申请日：2005-04-20
申请人： William Joseph Armstrong , Michael J. Corrigan , Naresh Nayar , Scott Barnett Swaney
发明人： William Joseph Armstrong , Michael J. Corrigan , Naresh Nayar , Scott Barnett Swaney
IPC分类号： G06F1/12
CPC分类号： G06F1/14
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to one of the processor cores for which the time base is determined. The time bases are synchronized together for the processor cores such that each one of the processor cores includes its own copy of a synchronized time base. For one of the processor cores, a virtualized time base is generated that is different from the synchronized time base but that remains synchronized with at least a portion of the synchronized time base. The processor core utilizes the virtualized time base instead of the synchronized time base for indicating the current time to the processor core. The synchronized time bases and the portion of the virtualized time base remaining in synchronization together.
摘要翻译：在用于在逻辑分区的数据处理系统中提供虚拟时基的数据处理系统中公开了一种方法，装置和计算机程序产品。为多个处理器核心中的每一个确定时基。时基用于指示当前时间到其中确定时基的一个处理器内核。对于处理器核心，时基同步在一起，使得每个处理器核心包括其自己的同步时基副本。对于其中一个处理器核心，生成与同步时基不同的虚拟时基，但与同步时基的至少一部分保持同步。处理器核心利用虚拟时基而不是同步的时基来指示处理器核心的当前时间。同步的时基和虚拟时基的一部分保持同步在一起。

2. 发明授权

US08019962B2 System and method for tracking the memory state of a migrating logical partition 有权
标题翻译：用于跟踪迁移逻辑分区的内存状态的系统和方法
公开(公告)号：US08019962B2
公开(公告)日：2011-09-13
申请号：US11735809
申请日：2007-04-16
申请人： William Joseph Armstrong , Michael J. Corrigan , Stuart Zachary Jacobs , David Anthony Larson , Naresh Nayar , Wade Byron Ouren
发明人： William Joseph Armstrong , Michael J. Corrigan , Stuart Zachary Jacobs , David Anthony Larson , Naresh Nayar , Wade Byron Ouren
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F9/4856 , G06F9/5077 , G06F12/08 , G06F12/1036 , G06F12/109
摘要： An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.
摘要翻译：用于跟踪迁移逻辑分区的状态的装置，程序产品和方法。实施例可以使用该状态来确定用于传送的逻辑分区的页面的准备和/或适当性。状态可以包括用于跟踪影响页面的变化的值或其他数据，或迁移页面的相对容易度和/或适当性。可以使用具有与逻辑分区的每个页面的状态对应的条目的页面管理器表来跟踪状态，同时逻辑分区在迁移期间继续运行。

3. 发明申请

US20080256321A1 System and Method for Tracking the Memory State of a Migrating Logical Partition 有权
标题翻译：跟踪迁移逻辑分区的内存状态的系统和方法
公开(公告)号：US20080256321A1
公开(公告)日：2008-10-16
申请号：US11735809
申请日：2007-04-16
申请人： William Joseph Armstrong , Michael J. Corrigan , Stuart Zachary Jacobs , David Anthony Larson , Naresh Nayar , Wade Byron Ouren
发明人： William Joseph Armstrong , Michael J. Corrigan , Stuart Zachary Jacobs , David Anthony Larson , Naresh Nayar , Wade Byron Ouren
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F9/4856 , G06F9/5077 , G06F12/08 , G06F12/1036 , G06F12/109
摘要： An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.
摘要翻译：用于跟踪迁移逻辑分区的状态的装置，程序产品和方法。实施例可以使用该状态来确定用于传送的逻辑分区的页面的准备和/或适当性。状态可以包括用于跟踪影响页面的变化的值或其他数据，或迁移页面的相对容易度和/或适当性。可以使用具有与逻辑分区的每个页面的状态对应的条目的页面管理器表来跟踪状态，同时逻辑分区在迁移期间继续运行。

4. 发明授权

US07822942B2 Selectively invalidating entries in an address translation cache 有权
标题翻译：选择性地使地址转换缓存中的条目无效
公开(公告)号：US07822942B2
公开(公告)日：2010-10-26
申请号：US12054538
申请日：2008-03-25
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F13/00
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

5. 发明申请

US20080168258A1 Method and Apparatus For Selecting the Architecture Level to Which a Processor Appears to Conform 有权
标题翻译：用于选择处理器符合的架构级别的方法和设备
公开(公告)号：US20080168258A1
公开(公告)日：2008-07-10
申请号：US11621393
申请日：2007-01-09
申请人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin
发明人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30101 , G06F9/30181 , G06F9/468
摘要： A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.
摘要翻译：一种用于在执行特定逻辑分区或程序并且在不同级别的处理器架构之间执行迁移时，选择处理器在计算环境内符合的架构级别的方法和系统。该方法利用“处理器兼容性寄存器”（PCR）来控制处理器似乎支持的架构级别。在一个实施方案中，PCR仅可用于超特权软件。超级特权软件设置PCR中的位，指定处理器将要支持的架构级别，以便当程序在处理器上运行时，处理器的行为与程序设计的架构级别相符。

6. 发明授权

US07389400B2 Apparatus and method for selectively invalidating entries in an address translation cache 有权
标题翻译：用于选择性地使地址转换高速缓存中的条目无效的装置和方法
公开(公告)号：US07389400B2
公开(公告)日：2008-06-17
申请号：US11304136
申请日：2005-12-15
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而地址转换高速缓存中的其他条目是无效的。

7. 发明授权

US07802252B2 Method and apparatus for selecting the architecture level to which a processor appears to conform 有权
标题翻译：用于选择处理器似乎符合的架构级别的方法和装置
公开(公告)号：US07802252B2
公开(公告)日：2010-09-21
申请号：US11621393
申请日：2007-01-09
申请人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin, II
发明人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin, II
IPC分类号： G06F9/46 , G06F9/50
CPC分类号： G06F9/30101 , G06F9/30181 , G06F9/468
摘要： A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.
摘要翻译：一种用于在执行特定逻辑分区或程序并且在不同级别的处理器架构之间执行迁移时，选择处理器在计算环境内符合的架构级别的方法和系统。该方法利用“处理器兼容性寄存器”（PCR）来控制处理器似乎支持的架构级别。在一个实施方案中，PCR仅可用于超特权软件。超级特权软件设置PCR中的位，指定处理器将要支持的架构级别，以便当程序在处理器上运行时，处理器的行为与程序设计的架构级别相符。

8. 发明申请

US20080168254A1 SELECTIVELY INVALIDATING ENTRIES IN AN ADDRESS TRANSLATION CACHE 有权
标题翻译：在地址翻译缓存中选择无效的入口
公开(公告)号：US20080168254A1
公开(公告)日：2008-07-10
申请号：US12054538
申请日：2008-03-25
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F9/34
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

9. 发明授权

US08209692B2 Deallocation of computer data in a multithreaded computer 失效
标题翻译：多线程计算机中计算机数据的分配
公开(公告)号：US08209692B2
公开(公告)日：2012-06-26
申请号：US11926967
申请日：2007-10-29
申请人： William Joseph Armstrong , Peter Joseph Heyrman , Naresh Nayar
发明人： William Joseph Armstrong , Peter Joseph Heyrman , Naresh Nayar
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/5016 , G06F9/5022 , Y10S707/99953 , Y10S707/99957
摘要： An apparatus, program product and method support the deallocation of a data structure in a multithreaded computer without requiring the use of computationally expensive semaphores or spin locks. Specifically, access to a data structure is governed by a shared pointer that, when a request is received to deallocate the data structure, is initially set to a value that indicates to any thread that later accesses the pointer that the data structure is not available. In addition, to address any thread that already holds a copy of the shared pointer, and thus is capable of accessing the data structure via the shared pointer after the initiation of the request, all such threads are monitored to determine whether any thread is still using the shared pointer by determining whether any thread is executing program code that is capable of using the shared pointer to access the data structure. Once this condition is met, it is ensured that no thread can potentially access the data structure via the shared pointer, and as such, the data structure may then be deallocated.
摘要翻译：一种装置，程序产品和方法支持多线程计算机中数据结构的释放，而不需要使用计算上昂贵的信号量或旋转锁。具体来说，访问数据结构由共享指针控制，当接收到请求以解除分配数据结构时，共享指针最初被设置为指示稍后访问指针的任何线程数据结构不可用的值。此外，为了解决已经拥有共享指针的副本的任何线程，并且因此能够在请求启动之后通过共享指针访问数据结构，所有这些线程被监视以确定是否有任何线程仍在使用该共享指针通过确定任何线程是否正在执行能够使用共享指针来访问数据结构的程序代码。一旦满足此条件，就确保没有线程可以通过共享指针潜在地访问数据结构，因此可以解除分配数据结构。

10. 发明授权

US08055838B2 Apparatus and method for autonomically suspending and resuming logical partitions when I/O reconfiguration is required 有权
标题翻译：需要I / O重新配置时，自动暂停和恢复逻辑分区的装置和方法
公开(公告)号：US08055838B2
公开(公告)日：2011-11-08
申请号：US10624808
申请日：2003-07-22
申请人： David Alan Bailey , William Joseph Armstrong , Naresh Nayar , Gregory Michael Nordstrom
发明人： David Alan Bailey , William Joseph Armstrong , Naresh Nayar , Gregory Michael Nordstrom
IPC分类号： G06F13/10
CPC分类号： G06F9/5077
摘要： A partition manager includes an I/O reconfiguration mechanism and a logical partition suspend/resume mechanism that work together to perform autonomic I/O reconfiguration in a logically partitioned computer system. When I/O reconfiguration is required, the affected logical partitions are suspended, the I/O is reconfigured, and the affected logical partitions are resumed. Because the logical partitions are suspended during I/O reconfiguration, any ghost packet that may occur when the I/O is reconfigured is ignored.
摘要翻译：分区管理器包括I / O重新配置机制和逻辑分区挂起/恢复机制，其协同工作以在逻辑分区的计算机系统中执行自主I / O重新配置。当需要I / O重新配置时，受影响的逻辑分区将被挂起，重新配置I / O，并恢复受影响的逻辑分区。因为逻辑分区在I / O重新配置期间被挂起，所以当I / O被重新配置时可能发生的任何ghost数据包被忽略。

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