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1. 发明授权

US08060719B2 Hybrid memory management 有权
标题翻译：混合内存管理
公开(公告)号：US08060719B2
公开(公告)日：2011-11-15
申请号：US12127945
申请日：2008-05-28
申请人： William H. Radke , Michael Murray , Martin Ragnar Furuhjelm , John Geldman
发明人： William H. Radke , Michael Murray , Martin Ragnar Furuhjelm , John Geldman
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F2212/1016 , G06F2212/1036 , G06F2212/7201 , G06F2212/7211 , G11C16/349 , G11C2211/5641
摘要： Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.
摘要翻译：用于使用单级和多级存储器单元来管理混合存储器件中的数据存储的方法和装置。逻辑地址可以基于执行的写操作的频率在单级和多级存储器单元之间分配。可以通过各种方法来确定与存储器中的逻辑地址相对应的数据的初始存储，包括首先将所有数据写入单级存储器或者首先将所有数据写入多级存储器。其他方法允许主机根据预期用途将逻辑地址写入指向单级或多级存储器单元。

2. 发明授权

US08296510B2 Hybrid memory management 有权
标题翻译：混合内存管理
公开(公告)号：US08296510B2
公开(公告)日：2012-10-23
申请号：US13295616
申请日：2011-11-14
申请人： William H. Radke , Michael Murray , Martin Ragnar Furuhjelm , John Geldman
发明人： William H. Radke , Michael Murray , Martin Ragnar Furuhjelm , John Geldman
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F2212/1016 , G06F2212/1036 , G06F2212/7201 , G06F2212/7211 , G11C16/349 , G11C2211/5641
摘要： Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.
摘要翻译：用于使用单级和多级存储器单元来管理混合存储器件中的数据存储的方法和装置。逻辑地址可以基于执行的写操作的频率在单级和多级存储器单元之间分配。可以通过各种方法来确定与存储器中的逻辑地址相对应的数据的初始存储，包括首先将所有数据写入单级存储器或者首先将所有数据写入多级存储器。其他方法允许主机根据预期用途将逻辑地址写入指向单级或多级存储器单元。

3. 发明申请

US20090300269A1 HYBRID MEMORY MANAGEMENT 有权
标题翻译：混合记忆管理
公开(公告)号：US20090300269A1
公开(公告)日：2009-12-03
申请号：US12127945
申请日：2008-05-28
申请人： William H. Radke , Michael Murray , Martin Ragnar Furuhjelm , John Geldman
发明人： William H. Radke , Michael Murray , Martin Ragnar Furuhjelm , John Geldman
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1016 , G06F2212/1036 , G06F2212/7201 , G06F2212/7211 , G11C16/349 , G11C2211/5641
摘要： Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.
摘要翻译：用于使用单级和多级存储器单元来管理混合存储器件中的数据存储的方法和装置。逻辑地址可以基于执行的写操作的频率在单级和多级存储器单元之间分配。可以通过各种方法来确定与存储器中的逻辑地址相对应的数据的初始存储，包括首先将所有数据写入单级存储器或者首先将所有数据写入多级存储器。其他方法允许主机根据预期用途将逻辑地址写入指向单级或多级存储器单元。

4. 发明授权

US08848478B2 Power consumption control 有权
标题翻译：功耗控制
公开(公告)号：US08848478B2
公开(公告)日：2014-09-30
申请号：US13625104
申请日：2012-09-24
申请人： Krishnam R. Datla , William H. Radke , Robin Sarno , Laszlo Borbely-Bartis , Ken Kannampuzha
发明人： Krishnam R. Datla , William H. Radke , Robin Sarno , Laszlo Borbely-Bartis , Ken Kannampuzha
IPC分类号： G11C5/14
CPC分类号： G06F3/0625 , G06F3/0653 , G06F3/0688 , G11C5/14 , G11C16/30
摘要： The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.
摘要翻译：本公开包括用于功耗控制的装置和方法。多个实施例包括在命令的相位组合中确定每个阶段的功率消耗信息，并且至少部分地基于至少为至少确定的功耗信息授权执行组合中的至少一个相位的功率消耗信息其中一个阶段。

5. 发明授权

US08762629B2 Data conditioning to improve flash memory reliability 有权
标题翻译：数据调理提高闪存的可靠性
公开(公告)号：US08762629B2
公开(公告)日：2014-06-24
申请号：US13616486
申请日：2012-09-14
申请人： William H. Radke , Vishal Sarin , Jung-Sheng Hoei
发明人： William H. Radke , Vishal Sarin , Jung-Sheng Hoei
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F11/1072 , G06F12/0246 , G06F2212/7205 , G06F2212/7208 , G11C11/5628 , G11C29/52 , G11C2211/5641
摘要： Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.
摘要翻译：用于利用不同密度存储单元的存储器阵列来管理存储器件中的数据存储的方法和装置。数据最初可以存储在较低密度的存储器中。可以将数据进一步读取，压缩，调节并写入高密度存储器作为后台操作。还公开了用于在存储到更高密度存储器期间提高数据可靠性的数据调节方法以及用于跨多个存储器阵列管理数据的方法。

6. 发明申请

US20140086000A1 POWER CONSUMPTION CONTROL 有权
标题翻译：功耗控制
公开(公告)号：US20140086000A1
公开(公告)日：2014-03-27
申请号：US13625104
申请日：2012-09-24
申请人： Krishnam R. Datla , William H. Radke , Robin Sarno , Laszlo Borbely-Bartis , Ken Kannampuzha
发明人： Krishnam R. Datla , William H. Radke , Robin Sarno , Laszlo Borbely-Bartis , Ken Kannampuzha
IPC分类号： G11C5/14
CPC分类号： G06F3/0625 , G06F3/0653 , G06F3/0688 , G11C5/14 , G11C16/30
摘要： The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.
摘要翻译：本公开包括用于功耗控制的装置和方法。多个实施例包括在命令的相位组合中确定每个阶段的功率消耗信息，并且至少部分地基于至少为至少确定的功耗信息授权执行组合中的至少一个相位的功率消耗信息其中一个阶段。

7. 发明授权

US08543802B2 Booting in systems having devices coupled in a chained configuration 有权
公开(公告)号：US08543802B2
公开(公告)日：2013-09-24
申请号：US13559162
申请日：2012-07-26
申请人： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
发明人： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
IPC分类号： G06F9/00 , G06F9/24 , G06F3/00
CPC分类号： G06F9/4411 , G06F9/4401
摘要： The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.

8. 发明授权

US08510634B2 Methods of data handling 有权
标题翻译：数据处理方法
公开(公告)号：US08510634B2
公开(公告)日：2013-08-13
申请号：US13371683
申请日：2012-02-13
申请人： Brady L. Keays , Shuba Swaminathan , William H. Radke
发明人： Brady L. Keays , Shuba Swaminathan , William H. Radke
IPC分类号： G11C29/00
CPC分类号： G06F11/10 , G06F11/1048 , H03M13/132 , H03M13/1515
摘要： Methods include receiving data and an ECC code read from a memory array, generating an ECC code from the received data, and determining whether the received data is corrupted by evaluating the generated ECC code against the ECC code read from the memory array. If the received data is determined to be corrupted, a correction algorithm and a recorded likely state of a known bad/questionable bit of the received data may be used to correct error in the received data. Alternatively, if the received data is determined to be corrupted, the correction algorithm and a recorded location of a known bad/questionable bit of the received data may be used to correct error in the received data.
摘要翻译：方法包括从存储器阵列接收数据和从其读取的ECC代码，从接收到的数据生成ECC代码，并且通过根据从存储器阵列读取的ECC代码评估所生成的ECC代码来确定接收的数据是否被破坏。如果接收到的数据被确定为被破坏，则可以使用接收到的数据的已知的坏/可疑比特的校正算法和记录的可能状态来校正接收到的数据中的错误。或者，如果接收到的数据被确定为已被破坏，则可以使用校正算法和接收到的数据的已知坏/可疑位的记录位置来校正接收到的数据中的错误。

9. 发明授权

US08468415B2 Error recovery storage along a memory string 有权
公开(公告)号：US08468415B2
公开(公告)日：2013-06-18
申请号：US13570180
申请日：2012-08-08
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F11/1072 , H03M13/256 , H03M13/2909
摘要： Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

10. 发明申请

US20130051143A1 MEMORY CELL COUPLING COMPENSATION 有权
标题翻译：记忆体耦合补偿
公开(公告)号：US20130051143A1
公开(公告)日：2013-02-28
申请号：US13215348
申请日：2011-08-23
申请人： Zhenlei Shen , William H. Radke , Peter Feeley
发明人： Zhenlei Shen , William H. Radke , Peter Feeley
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G06F11/1068 , G06F11/1004 , G06F11/1048 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C29/04 , G11C29/52
摘要： Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.
摘要翻译：描述了用于存储器单元耦合补偿的方法和被配置为执行其的装置。用于存储单元耦合补偿的一种或多种方法包括使用根据第一存储单元耦合补偿电压而改变的电压来确定存储单元的状态，对存储单元的状态执行错误检查，以及确定状态使用响应于错误检查失败的根据第二存储器单元耦合补偿电压而改变的电压的存储器单元。

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