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1. 发明授权

US5291494A Method of handling errors in software 失效
标题翻译：处理软件错误的方法
公开(公告)号：US5291494A
公开(公告)日：1994-03-01
申请号：US978053
申请日：1992-11-18
申请人： William F. Bruckert , Thomas D. Bissett , James Melvin
发明人： William F. Bruckert , Thomas D. Bissett , James Melvin
IPC分类号： G06F11/20 , G06F11/00 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/22 , G06F11/28 , G06F11/34 , G06F12/08
CPC分类号： G06F11/1633 , G06F11/0724 , G06F11/0793 , G06F11/165 , G06F11/10 , G06F11/1008 , G06F11/1415 , G06F11/20 , G06F11/2205 , G06F11/34
摘要： The software error handling determines the nature of the fault and takes different action depending upon the nature of the fault. If the fault prevents the data processing system from continued reliable operation, then the element causing the fault is immediately disabled. Otherwise, the element which is the source of the fault is treated so that it does no harm to the system and causes no further faults. The element can then be completely handled during normal software status checks.
摘要翻译：软件错误处理决定了故障的性质，并根据故障的性质采取不同的行动。如果故障防止数据处理系统继续可靠运行，则导致故障的元件立即被禁用。否则，处理故障来源的元素不会对系统造成危害，不会导致进一步的故障。然后可以在正常的软件状态检查期间完全处理该元素。

2. 发明授权

US5153881A Method of handling errors in software 失效
标题翻译：在软件中处理错误的方法
公开(公告)号：US5153881A
公开(公告)日：1992-10-06
申请号：US388041
申请日：1989-08-01
申请人： William F. Bruckert , Thomas D. Bissett , James Melvin
发明人： William F. Bruckert , Thomas D. Bissett , James Melvin
IPC分类号： G06F11/20 , G06F9/445 , G06F11/00 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/22 , G06F11/34
CPC分类号： G06F11/1633 , G06F11/0712 , G06F11/0724 , G06F11/165 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1415 , G06F11/20 , G06F11/2205 , G06F11/34
摘要： Hardware error processing is undertaken to analyze the source of the error and to preserve sufficient information to allow later software error processing. The hardware error processing also allows, for certain errors, complete recovery without interruption of the sequence of instruction execution.

3. 发明授权

US4862465A Dual-rail processors with error checking on I/O reads 失效
公开(公告)号：US4862465A
公开(公告)日：1989-08-29
申请号：US093495
申请日：1987-09-04
申请人： William F. Bruckert , Thomas D. Bissett
发明人： William F. Bruckert , Thomas D. Bissett
摘要： A dual processor data processing system having interprocessor error checking includes a first central processing unit executing a series of instructions. A second central processing unit executes the same series of instructions independently of and in synchronism with the first central processing unit. A first data bus is coupled to the first central processing unit for receiving data to be input to the first central processing unit and a second data bus is coupled to the second central processing unit for receiving data to be input to the second central processing unit. Error checking devices are coupled to the first and second data busses for checking data transmitted over the first and second data busses and for detecting errors on I/O reads prior to delivery of the data to the first and second central processing units. The error checking devices include comparison means for indicating an error when the data on the first and second data busses are unequal. Error isolation devices are responsive to an error detected from the error checking means for analyzing the cause of error while maintaining system synchronization.

4. 发明授权

US4916704A Interface of non-fault tolerant components to fault tolerant system 失效
标题翻译：非容错组件到容错系统的接口
公开(公告)号：US4916704A
公开(公告)日：1990-04-10
申请号：US93539
申请日：1987-09-04
申请人： William F. Bruckert , Thomas D. Bissett , Mitchell O. Norcross , Kenneth A. Ward
发明人： William F. Bruckert , Thomas D. Bissett , Mitchell O. Norcross , Kenneth A. Ward
IPC分类号： G06F11/18 , G06F9/445 , G06F11/00 , G06F11/08 , G06F11/10 , G06F11/14 , G06F11/22 , G06F11/267
CPC分类号： G06F11/165 , G06F11/0724 , G06F11/076 , G06F11/1658 , G06F11/1666 , G06F11/2017 , G06F11/004 , G06F11/08 , G06F11/10 , G06F11/1044 , G06F11/2205 , G06F11/2236 , G06F2201/845
摘要： A fault tolerant computer system includes a fault tolerant data processing module which has means for detecting and correcting errors in the operation of the data processing module to maintain a high degree of data integrity. Data transmission control devices control the transmission of all data to the fault tolerant data processing module and the receipt of all data into the fault tolerant data processing module. Input/output terminals are coupled to the data transmission control means for receiving and transmitting data. A non-fault tolerant input/output module is coupled to transmit the data to the input/output terminals of the fault tolerant data processing module. This module includes a read device for transferring data to the fault tolerant computing system in response to requests from the data transmission control devices, and a firewall for preventing the non-fault tolerant input/output module from initiating transfers of data to the fault tolerant data processing module.

5. 发明授权

US4907228A Dual-rail processor with error checking at single rail interfaces 失效
标题翻译：双轨处理器，在单轨接口进行错误检查
公开(公告)号：US4907228A
公开(公告)日：1990-03-06
申请号：US93584
申请日：1987-09-04
申请人： William F. Bruckert , Thomas D. Bissett , Norbert H. Riegelhaupt
发明人： William F. Bruckert , Thomas D. Bissett , Norbert H. Riegelhaupt
IPC分类号： G06F11/18 , G06F11/10 , G06F11/16
CPC分类号： G06F11/1633 , G06F11/165 , G06F11/10
摘要： A dual processor computer system with error checking includes a first processing system for executing a series of instructions including output instructions. A second processing system executes the series of instructions independently of and in synchronism with the first processing system. Shared resource devices are coupled to the first and second processing systems for receiving data from output instructions from the first and second processing systems substantially simultaneously. Error checking devices are located downstream of the shared resource means for checking the data received from the first and second processing systems only following a write operation into the shared resource means.

6. 发明授权

US5249187A Dual rail processors with error checking on I/O reads 失效
标题翻译：双轨处理器，对I / O读取进行错误检查
公开(公告)号：US5249187A
公开(公告)日：1993-09-28
申请号：US357613
申请日：1989-05-25
申请人： William F. Bruckert , Thomas D. Bissett
发明人： William F. Bruckert , Thomas D. Bissett
IPC分类号： G06F9/445 , G06F11/00 , G06F11/08 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/22 , G06F11/267
CPC分类号： G06F11/1633 , G06F11/165 , G06F11/1675 , G06F11/2035 , G06F11/076 , G06F11/08 , G06F11/14 , G06F11/2043 , G06F11/2205 , G06F11/2236
摘要： A dual processor data processing system having interprocessor error checking includes a first central processing unit executing a series of instructions. A second central processing unit executes the same series of instructions independently of and in synchronism with the first central processing unit. A first data bus is coupled to the first central processing unit for receiving data to be input to the first central processing unit and a second data bus is coupled to the second central processing unit for receiving data to be input to the second central processing unit. Error checking devices are coupled to the first and second data busses for checking data transmitted over the first and second data busses and for detecting errors on I/O reads prior to delivery of the data to the first and second central processing units. The error checking devices include comparison means for indicating an error when the data on the first and second data busses are unequal. Error isolation devices are responsive to an error detected from the error checking means for analyzing the cause of error while maintaining system synchronization.
摘要翻译：具有处理器间错误检查的双处理器数据处理系统包括执行一系列指令的第一中央处理单元。第二中央处理单元独立于第一中央处理单元执行相同的指令序列，并且与第一中央处理单元同步执行。第一数据总线耦合到第一中央处理单元，用于接收要输入到第一中央处理单元的数据，第二数据总线耦合到第二中央处理单元，用于接收要输入到第二中央处理单元的数据。错误检查设备被耦合到第一和第二数据总线，用于检查通过第一和第二数据总线传输的数据，并且用于在将数据传送到第一和第二中央处理单元之前检测I / O读取上的错误。错误检查装置包括用于在第一和第二数据总线上的数据不相等时指示错误的比较装置。错误隔离装置响应于从错误检查装置检测到的错误，用于在维护系统同步的同时分析错误原因。

7. 发明授权

US5255367A Fault tolerant, synchronized twin computer system with error checking of I/O communication 失效
标题翻译：容错同步双计算机系统，具有I / O通信的错误检查
公开(公告)号：US5255367A
公开(公告)日：1993-10-19
申请号：US382023
申请日：1989-07-19
申请人： William F. Bruckert , Thomas D. Bissett , Dennis Mazur , John Munzer
发明人： William F. Bruckert , Thomas D. Bissett , Dennis Mazur , John Munzer
IPC分类号： G06F11/18 , G06F1/12 , G06F1/16 , G06F11/00 , G06F11/08 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/20 , G06F11/22
CPC分类号： G06F1/12 , G06F1/16 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/076 , G06F11/0796 , G06F11/08 , G06F11/10 , G06F11/1044 , G06F11/14 , G06F11/22 , G06F11/2205 , G06F2201/88
摘要： A dual processor computer system includes a first processing system having a central processing unit which executes a series of data processing instructions, a data bus system for transferring data to and from the first central processing unit, a memory unit coupled to the first central processing unit, and a cross-link communications element for transferring data into and out of the first processing system. A similarly configured second processing system, operating independently of the first processing system, is also provided. The cross-link communications element associated with the second processing system is coupled to the cross-link communication element of the first processing system, for transferring data into the second processing system from the first processing system and for transferring data into the first processing system from the second computer system.
摘要翻译：双处理器计算机系统包括具有执行一系列数据处理指令的中央处理单元的第一处理系统，用于向和从第一中央处理单元传送数据的数据总线系统，耦合到第一中央处理单元的存储单元以及用于将数据传入和传出第一处理系统的交叉链路通信元件。还提供了独立于第一处理系统操作的类似配置的第二处理系统。与第二处理系统相关联的交叉链路通信元件耦合到第一处理系统的交叉链路通信元件，用于从第一处理系统将数据传送到第二处理系统，并将数据从第一处理系统传送到第一处理系统第二台电脑系统。

8. 发明授权

US5099485A Fault tolerant computer systems with fault isolation and repair 失效
标题翻译：具有故障隔离和修复的容错计算机系统
公开(公告)号：US5099485A
公开(公告)日：1992-03-24
申请号：US357626
申请日：1989-05-25
申请人： William F. Bruckert , Thomas D. Bissett , Dennis Mazur , John Munzer , Frank Bernaby , Jay H. Bhatia
发明人： William F. Bruckert , Thomas D. Bissett , Dennis Mazur , John Munzer , Frank Bernaby , Jay H. Bhatia
IPC分类号： G06F11/16 , G06F11/00 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/18 , G06F11/20 , G06F11/22
CPC分类号： G06F11/1633 , G06F11/0724 , G06F11/0727 , G06F11/079 , G06F11/142 , G06F11/16 , G06F11/165 , G06F11/076 , G06F11/10 , G06F11/1008 , G06F11/1658 , G06F11/20 , G06F11/2097 , G06F11/2205 , G06F2201/845
摘要： A fault tolerant computer system has a central processing system which includes at least one set of data pathways, and executes a series of data processing instructions including the transfer of messages along the plurality of data pathways. At least one set of transaction data storage devices are coupled to the data pathways for storing a predetermined number of successive messages transferred most recently on the data pathways. Error checking devices are included for detecting the presence of errors in the central processing system. Error storage devices are coupled to the transaction data storage devices and the error checking devices for causing the transaction data storage devices to cease storing additional messages in response to the detection of errors by the error checking device.
摘要翻译：容错计算机系统具有包括至少一组数据路径的中央处理系统，并且执行一系列数据处理指令，包括沿多个数据路径的消息传送。至少一组交易数据存储设备耦合到数据路径，用于存储最近在数据路径上传送的预定数量的连续消息。包括错误检查设备，用于检测中央处理系统中是否存在错误。错误存储设备耦合到事务数据存储设备和错误检查设备，用于使交易数据存储设备响应错误检测设备的错误检测而停止存储附加消息。

9. 发明授权

US5005174A Dual zone, fault tolerant computer system with error checking in I/O writes 失效
标题翻译：双区域，容错计算机系统，在I / O写入中进行错误检查
公开(公告)号：US5005174A
公开(公告)日：1991-04-02
申请号：US489751
申请日：1990-02-26
申请人： William F. Bruckert , Thomas D. Bissett
发明人： William F. Bruckert , Thomas D. Bissett
IPC分类号： G06F11/18 , G06F1/12 , G06F1/16 , G06F11/00 , G06F11/08 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/20 , G06F11/22
CPC分类号： G06F1/12 , G06F1/16 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/076 , G06F11/0796 , G06F11/08 , G06F11/10 , G06F11/1044 , G06F11/14 , G06F11/22 , G06F11/2205 , G06F2201/88
摘要： A fault tolerant computer system having a first processing system which includes a first data processor for executing a series of data processing instructions. A first data output terminal outputs data from the first processing system. A second processing system, substantially identical to the first processing system, operates independently from the first processing system. The second processing system includes a second data processor for executing the series of data processing instructions in the same sequence as the first data processor. It also includes a second data output terminal for outputting data from the second processing system. A synchronizing device is coupled to the first and second data processors for maintaining the execution of the series of data processing instructions by the first and second processing systems in synchronism. Fault detection devices are coupled to the first and second data output terminals for comparing the data output from the first processing system with the data output from the second processing system. The fault detection devices identify the presence of an error when the data output from the first processing system at the first output terminal is different from the data output from the second processing system at the second output terminal.
摘要翻译：一种具有第一处理系统的容错计算机系统，其包括用于执行一系列数据处理指令的第一数据处理器。第一数据输出端子从第一处理系统输出数据。基本上与第一处理系统相同的第二处理系统独立于第一处理系统工作。第二处理系统包括用于以与第一数据处理器相同的顺序执行一系列数据处理指令的第二数据处理器。它还包括用于从第二处理系统输出数据的第二数据输出端。同步装置耦合到第一和第二数据处理器，用于同步地由第一和第二处理系统维持一系列数据处理指令的执行。故障检测装置耦合到第一和第二数据输出端，用于将从第一处理系统输出的数据与从第二处理系统输出的数据进行比较。当从第一输出端子的第一处理系统输出的数据与在第二输出端子处从第二处理系统输出的数据不同时，故障检测装置识别出现错误。

10. 发明授权

US5600784A Fault resilient/fault tolerant computing 失效
标题翻译：故障恢复/容错计算
公开(公告)号：US5600784A
公开(公告)日：1997-02-04
申请号：US405193
申请日：1995-03-16
申请人： Thomas D. Bissett , Richard D. Fiorentino , Robert M. Glorioso , Diane T. McCauley , James D. McCollum , Glenn A. Tremblay
发明人： Thomas D. Bissett , Richard D. Fiorentino , Robert M. Glorioso , Diane T. McCauley , James D. McCollum , Glenn A. Tremblay
IPC分类号： G06F11/18 , G06F1/04 , G06F1/14 , G06F11/00 , G06F11/14 , G06F11/16 , G06F11/20 , G06F13/00 , G06F13/10 , G06F13/14 , G06F15/16 , G06F15/76 , G01R31/28
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/2005 , G06F11/2017 , G06F11/1641 , G06F11/185
摘要： In a first aspect, a method of synchronizing at least two computing elements that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements, monitoring the computing elements to detect the production of a selected signal by one of the computing elements, waiting for the other computing elements to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements based on the time updates.In a second aspect, fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing elements.Computer systems include one or more controllers and at least two computing elements. System is provided for intercepting I/O operations by the computing elements and transmitting them to the one or more controllers.
摘要翻译：在第一方面中，一种同步至少两个计算元件的方法，每个计算元件具有与其它计算元件的时钟异步工作的时钟，包括从由所述另一个计算元件产生的一组信号中选择一个或多个指定为元时间信号的信号计算元件，监视所述计算元件以通过所述计算元件之一检测所选择的信号的产生，等待所述其他计算元件产生所选择的信号，向所述计算元件中的每一个发送等价的时间更新，以及更新所述时钟的计算元素基于时间更新。在第二方面，通过将第一处理器指定为计算元件，指定作为控制器的第二处理器，连接计算元件和控制器以产生模块对，并连接至少两个模块化成对产生故障恢复或容错计算机。计算机的每个计算元件执行与其它计算元件相同数量的循环的所有指令。计算机系统包括一个或多个控制器和至少两个计算元件。提供系统用于通过计算元件截取I / O操作并将其发送到一个或多个控制器。

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