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1. 发明申请

US20070057679A1 Calibration method and system 有权
标题翻译：校准方法和系统
公开(公告)号：US20070057679A1
公开(公告)日：2007-03-15
申请号：US11224642
申请日：2005-09-12
申请人： William Ellersick , Jennifer Lloyd , Daniel Mulcahy
发明人： William Ellersick , Jennifer Lloyd , Daniel Mulcahy
IPC分类号： G01R35/00
CPC分类号： H03H7/0153 , H03H2210/021 , H03H2210/043
摘要： A system and method of calibration develops a function from which is generated a monotonic time response; a gating period is defined from the monotonic time response and any error in the frequency of a reference signal is determined during the gating period; from that error an error signal is generated for adjusting the time constant of a circuit to be calibrated.
摘要翻译：校准的系统和方法产生一个函数，由此产生单调时间响应; 从单调时间响应定义门控周期，并且在选通期间确定参考信号频率的任何误差; 从该误差产生用于调整要校准的电路的时间常数的误差信号。

2. 发明申请

US20130043937A1 APPARATUS AND METHOD FOR ELECTRICAL BIASING 有权
标题翻译：电气偏置的装置和方法
公开(公告)号：US20130043937A1
公开(公告)日：2013-02-21
申请号：US13586544
申请日：2012-08-15
申请人： Jennifer Lloyd , Kimo Tam
发明人： Jennifer Lloyd , Kimo Tam
IPC分类号： G05F1/10
CPC分类号： H03F1/30 , H03F1/0283 , H03F2200/18 , H03K19/0008
摘要： As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point.
摘要翻译：如本文所提供的，在一些实施例中，通过被配置为为多于一个有源电路提供偏置条件的偏置电路来降低功耗和/或芯片面积，从而减少设计中偏置电路的数量。共享偏置电路可以减少由偏置电路使用的片上区域的总量，并且还可以降低芯片的总功耗。附加地和/或替代地，本文公开的偏置电路被配置为提供对电压供应电平的变化较不敏感的输出。特别地，在一些实施例中，偏置电路被配置为提供相对恒定的偏置条件，尽管电压电平的变化。在一些实施例中，偏置电路被配置为提供补偿由改变其他输入引起的扰动的偏置条件，以便稳定特定的工作点。

3. 发明申请

US20120049941A1 APPARATUS AND METHOD CONFIGURED TO PROVIDE ELECTRICAL BIAS 有权
标题翻译：设备和方法配置提供电气偏差
公开(公告)号：US20120049941A1
公开(公告)日：2012-03-01
申请号：US12862171
申请日：2010-08-24
申请人： Jennifer Lloyd , Kimo Tam
发明人： Jennifer Lloyd , Kimo Tam
IPC分类号： G05F1/10
CPC分类号： H03F1/30 , H03F1/0283 , H03F2200/18 , H03K19/0008
摘要： As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. A bias circuit arrangement with an output substantially decoupled from changes in the voltage supply level may provide a more stable operating point in an active circuit. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point.
摘要翻译：如本文所提供的，在一些实施例中，通过被配置为为多于一个有源电路提供偏置条件的偏置电路来降低功耗和/或芯片面积，从而减少设计中偏置电路的数量。共享偏置电路可以减少由偏置电路使用的片上区域的总量，并且还可以降低芯片的总功耗。附加地和/或替代地，本文公开的偏置电路被配置为提供对电压供应电平的变化较不敏感的输出。特别地，在一些实施例中，偏置电路被配置为提供相对恒定的偏置条件，尽管电压电平的变化。具有与电压供应电平的变化基本上分离的输出的偏置电路装置可以在有源电路中提供更稳定的工作点。在一些实施例中，偏置电路被配置为提供补偿由改变其他输入引起的扰动的偏置条件，以便稳定特定的工作点。

4. 发明授权

US08680938B2 Apparatus and method for equalization 有权
标题翻译：用于均衡的装置和方法
公开(公告)号：US08680938B2
公开(公告)日：2014-03-25
申请号：US13093372
申请日：2011-04-25
申请人： Michael St. Germain , Jennifer Lloyd , Kimo Tam
发明人： Michael St. Germain , Jennifer Lloyd , Kimo Tam
IPC分类号： H04B3/14 , H03F3/45
CPC分类号： H03F3/4508 , H03F2203/45458 , H03F2203/45476 , H03F2203/45544 , H03F2203/45696 , H03F2203/45726
摘要： Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor.
摘要翻译：提供了用于均衡的装置和方法。在一个实施例中，用于均衡输入电压的装置包括第一电容器和具有第一端和第二端的第一电阻器，第一端被配置为接收输入电压。该装置还包括第二电阻器，其具有在输出节点处电连接到第一电阻器的第二端的第一端。该装置还包括用于基本上反相输入电压以产生反相输入电压的反相电压缓冲器。该装置还包括跨导缓冲器，用于接收反相输入电压，并用于从第一电容器的第一端向输出节点产生电流，其大小等于输入电压信号的幅度除以第一电容器的阻抗电容器。

5. 发明授权

US08248151B2 Apparatus and method configured to provide electrical bias 有权
标题翻译：配置为提供电偏压的装置和方法
公开(公告)号：US08248151B2
公开(公告)日：2012-08-21
申请号：US12862171
申请日：2010-08-24
申请人： Jennifer Lloyd , Kimo Tam
发明人： Jennifer Lloyd , Kimo Tam
IPC分类号： G05F1/10
CPC分类号： H03F1/30 , H03F1/0283 , H03F2200/18 , H03K19/0008
摘要： As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. A bias circuit arrangement with an output substantially decoupled from changes in the voltage supply level may provide a more stable operating point in an active circuit. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point.
摘要翻译：如本文所提供的，在一些实施例中，通过被配置为为多于一个有源电路提供偏置条件的偏置电路来降低功耗和/或芯片面积，从而减少设计中偏置电路的数量。共享偏置电路可以减少由偏置电路使用的片上区域的总量，并且还可以降低芯片的总功耗。附加地和/或替代地，本文公开的偏置电路被配置为提供对电压供应电平的变化较不敏感的输出。特别地，在一些实施例中，偏置电路被配置为提供相对恒定的偏置条件，尽管电压电平的变化。具有与电压供应电平的变化基本上分离的输出的偏置电路装置可以在有源电路中提供更稳定的工作点。在一些实施例中，偏置电路被配置为提供补偿由改变其他输入引起的扰动的偏置条件，以便稳定特定的工作点。

6. 发明授权

US08106700B2 Wideband voltage translators 有权
标题翻译：宽带电压转换器
公开(公告)号：US08106700B2
公开(公告)日：2012-01-31
申请号：US12503372
申请日：2009-07-15
申请人： Kimo Y. F. Tam , Jennifer Lloyd
发明人： Kimo Y. F. Tam , Jennifer Lloyd
IPC分类号： H03L5/00
CPC分类号： H03F3/505 , H03F3/211 , H03F3/45206 , H03F3/45304 , H03F2200/168 , H03F2200/171 , H03F2200/36 , H03F2200/39 , H03F2200/429 , H03F2200/451 , H03F2203/21142 , H03F2203/21157 , H03F2203/45468 , H03F2203/45631 , H03F2203/45638 , H03F2203/45656 , H03F2203/45701 , H03F2203/45702 , H03F2203/5033
摘要： In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth.
摘要翻译：在本发明的实施例中，常规电压转换器中的低频响应差，低速度，高成本和高功耗的问题通过在两个并联级分别处理输入信号的高频和低频分量来解决，而没有使用大型无源元件或慢速器件。在输出端，经处理的高频和低频分量在组合阶段无缝地合并，通过整个转换器带宽维持频率响应的完整性。

7. 发明申请

US20060128771A1 Method of treating acne 审中-公开
公开(公告)号：US20060128771A1
公开(公告)日：2006-06-15
申请号：US11202014
申请日：2005-08-11
申请人： Mirko Mirkov , Jennifer Lloyd
发明人： Mirko Mirkov , Jennifer Lloyd
IPC分类号： A61K31/427 , A61K31/405 , A61N1/30
CPC分类号： A61N5/062 , A61B18/203 , A61B2018/00452 , A61N5/0616 , A61N2005/067
摘要： A method of selectively enhancing photothermal sebaceous gland disruption and treatment of acne is disclosed. The method provides for alleviation of the acne symptoms as well as preventing acne recurrence and new acne from occurring.

8. 发明授权

US08508286B2 Apparatus and method for electrical biasing 有权
标题翻译：用于电气偏置的装置和方法
公开(公告)号：US08508286B2
公开(公告)日：2013-08-13
申请号：US13586544
申请日：2012-08-15
申请人： Jennifer Lloyd , Kimo Tam
发明人： Jennifer Lloyd , Kimo Tam
IPC分类号： G05F1/10
CPC分类号： H03F1/30 , H03F1/0283 , H03F2200/18 , H03K19/0008
摘要： As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point.
摘要翻译：如本文所提供的，在一些实施例中，通过被配置为为多于一个有源电路提供偏置条件的偏置电路来降低功耗和/或芯片面积，从而减少设计中偏置电路的数量。共享偏置电路可以减少由偏置电路使用的片上区域的总量，并且还可以降低芯片的总功耗。附加地和/或替代地，本文公开的偏置电路被配置为提供对电压供应电平的变化较不敏感的输出。特别地，在一些实施例中，偏置电路被配置为提供相对恒定的偏置条件，尽管电压电平的变化。在一些实施例中，偏置电路被配置为提供补偿由改变其他输入引起的扰动的偏置条件，以便稳定特定的工作点。

9. 发明申请

US20120268204A1 APPARATUS AND METHOD FOR EQUALIZATION 有权
标题翻译：用于均衡的装置和方法
公开(公告)号：US20120268204A1
公开(公告)日：2012-10-25
申请号：US13093372
申请日：2011-04-25
申请人： Michael St. Germain , Jennifer Lloyd , Kimo Tam
发明人： Michael St. Germain , Jennifer Lloyd , Kimo Tam
IPC分类号： H03F3/45
CPC分类号： H03F3/4508 , H03F2203/45458 , H03F2203/45476 , H03F2203/45544 , H03F2203/45696 , H03F2203/45726
摘要： Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor.
摘要翻译：提供了用于均衡的装置和方法。在一个实施例中，用于均衡输入电压的装置包括第一电容器和具有第一端和第二端的第一电阻器，第一端被配置为接收输入电压。该装置还包括第二电阻器，其具有在输出节点处电连接到第一电阻器的第二端的第一端。该装置还包括用于基本上反相输入电压以产生反相输入电压的反相电压缓冲器。该装置还包括跨导缓冲器，用于接收反相输入电压，并用于从第一电容器的第一端向输出节点产生电流，其大小等于输入电压信号的幅度除以第一电容器的阻抗电容器。

10. 发明申请

US20100277215A1 Wideband Voltage Translators 有权
标题翻译：宽带电压转换器
公开(公告)号：US20100277215A1
公开(公告)日：2010-11-04
申请号：US12503372
申请日：2009-07-15
申请人： Kimo Y.F. Tam , Jennifer Lloyd
发明人： Kimo Y.F. Tam , Jennifer Lloyd
IPC分类号： H03L5/00 , G06G7/12
CPC分类号： H03F3/505 , H03F3/211 , H03F3/45206 , H03F3/45304 , H03F2200/168 , H03F2200/171 , H03F2200/36 , H03F2200/39 , H03F2200/429 , H03F2200/451 , H03F2203/21142 , H03F2203/21157 , H03F2203/45468 , H03F2203/45631 , H03F2203/45638 , H03F2203/45656 , H03F2203/45701 , H03F2203/45702 , H03F2203/5033
摘要： In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth.
摘要翻译：在本发明的实施例中，常规电压转换器中的低频响应差，低速度，高成本和高功耗的问题通过在两个并联级分别处理输入信号的高频和低频分量来解决，而没有使用大型无源元件或慢速器件。在输出端，经处理的高频和低频分量在组合阶段无缝地合并，通过整个转换器带宽维持频率响应的完整性。

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