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1. 发明授权

US08041928B2 Information handling system with real and virtual load/store instruction issue queue 有权
标题翻译：具有实际和虚拟加载/存储指令问题队列的信息处理系统
公开(公告)号：US08041928B2
公开(公告)日：2011-10-18
申请号：US12341930
申请日：2008-12-22
申请人： William E. Burky , Kurt A. Feiste , Dung Quoc Nguyen , Balaram Sinharoy , Albert Thomas Williams
发明人： William E. Burky , Kurt A. Feiste , Dung Quoc Nguyen , Balaram Sinharoy , Albert Thomas Williams
IPC分类号： G06F9/00
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3851
摘要： An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.
摘要翻译：信息处理系统包括可执行发布队列虚拟加载/存储指令操作的处理器。问题队列通过实际/虚拟依赖标志来维护加载和存储指令。问题队列为实际和虚拟加载/存储指令提供存储资源。实际加载/存储指令在加载存储单元LSU中执行。虚拟加载/存储指令正在等待在LSU中执行。 LSU可以通过线程，类型和指针数据跟踪发布队列内的每个虚拟加载/存储指令。假设所有依赖关系对待处理的虚拟加载/存储指令都是清楚的，则LSU将待处理的虚拟加载/存储指令标记为真实的。然后，挂起的虚拟加载/存储指令可以作为实际加载/存储指令发布到LSU。

2. 发明申请

US20100161945A1 INFORMATION HANDLING SYSTEM WITH REAL AND VIRTUAL LOAD/STORE INSTRUCTION ISSUE QUEUE 有权
标题翻译：信息处理系统与真实和虚拟负载/存储指导问题队列
公开(公告)号：US20100161945A1
公开(公告)日：2010-06-24
申请号：US12341930
申请日：2008-12-22
申请人： William E. Burky , Kurt A. Feiste , Dung Quoc Nguyen , Balaram Sinharoy , Albert Thomas Williams
发明人： William E. Burky , Kurt A. Feiste , Dung Quoc Nguyen , Balaram Sinharoy , Albert Thomas Williams
IPC分类号： G06F9/312
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3851
摘要： An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.
摘要翻译：信息处理系统包括可执行发布队列虚拟加载/存储指令操作的处理器。问题队列通过实际/虚拟依赖标志来维护加载和存储指令。问题队列为实际和虚拟加载/存储指令提供存储资源。实际加载/存储指令在加载存储单元LSU中执行。虚拟加载/存储指令正在等待在LSU中执行。 LSU可以通过线程，类型和指针数据跟踪发布队列内的每个虚拟加载/存储指令。假设所有依赖关系对待处理的虚拟加载/存储指令都是清楚的，则LSU将待处理的虚拟加载/存储指令标记为真实的。然后，挂起的虚拟加载/存储指令可以作为实际加载/存储指令发布到LSU。

3. 发明授权

US08418180B2 Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
标题翻译：线程优先级方法，用于确保同时多线程微处理器的处理公平性
公开(公告)号：US08418180B2
公开(公告)日：2013-04-09
申请号：US12129876
申请日：2008-05-30
申请人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
发明人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4818 , G06F9/485
摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.
摘要翻译：公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

4. 发明申请

US20100250900A1 DEPENDENCY TRACKING FOR ENABLING SUCCESSIVE PROCESSOR INSTRUCTIONS TO ISSUE 有权
标题翻译：用于启用后续处理器指令的依赖跟踪
公开(公告)号：US20100250900A1
公开(公告)日：2010-09-30
申请号：US12409934
申请日：2009-03-24
申请人： Mary Douglass Brown , William Elton Burky , Dung Quoc Nguyen , Balaram Sinharoy
发明人： Mary Douglass Brown , William Elton Burky , Dung Quoc Nguyen , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3814 , G06F9/3838
摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.
摘要翻译：信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。

5. 发明申请

US20080250226A1 Multi-Mode Register Rename Mechanism for a Highly Threaded Simultaneous Multi-Threaded Microprocessor 有权
标题翻译：多线程同时多线程微处理器的多模式寄存器重命名机制
公开(公告)号：US20080250226A1
公开(公告)日：2008-10-09
申请号：US11696363
申请日：2007-04-04
申请人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
发明人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F9/30145 , G06F9/30189 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3885
摘要： A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.
摘要翻译：多模式寄存器重命名机制，允许同时多线程处理器在线程数量低时支持完全无序的线程执行，并且当线程数增加时按顺序执行线程。响应于改变处理器的执行模式以按顺序执行线程执行模式，所述说明性实施例将数据处理系统中的物理寄存器切换到架构设施，从而形成切换的物理寄存器。当向执行单元发出指令时，其中发出的指令包括一个线程位，检查该线程位以确定该指令是否访问一个架构设施。如果发出的指令访问架构设施，则执行该指令，并且将所执行的指令的结果写入切换的物理寄存器。

6. 发明申请

US20080229065A1 Configurable Microprocessor 审中-公开
标题翻译：可配置微处理器
公开(公告)号：US20080229065A1
公开(公告)日：2008-09-18
申请号：US11685428
申请日：2007-03-13
申请人： Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
发明人： Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3012 , G06F9/3013 , G06F9/3814 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3885 , G06F9/3891 , G06F9/5061 , G06F2209/5012
摘要： A configurable microprocessor which combines a plurality of corelets into a single microprocessor core to handle high computing-intensive workloads. The process first selects two or more corelets in the plurality of corelets. The process combines resources of the two or more corelets to form combined resources, wherein each combined resource comprises a larger amount of a resource available to each individual corelet. The process then forms a single microprocessor core from the two or more corelets by assigning the combined resources to the single microprocessor core, wherein the combined resources are dedicated to the single microprocessor core, and wherein the single microprocessor core processes instructions with the dedicated combined resources.
摘要翻译：一种可配置的微处理器，将多个核心组合成单个微处理器核心，以处理高计算密集型工作负载。该过程首先在多个核心中选择两个或更多个核心。该过程组合两个或更多个核心小区的资源以形成组合的资源，其中每个组合的资源包括更大量的可用于每个单个小堆的资源。然后，该过程通过将组合的资源分配给单个微处理器核心而从两个或更多个核心小区形成单个微处理器核心，其中组合资源专用于单个微处理器核心，并且其中单个微处理器核心使用专用组合资源来处理指令。

7. 发明申请

US20080229058A1 Configurable Microprocessor 审中-公开
标题翻译：可配置微处理器
公开(公告)号：US20080229058A1
公开(公告)日：2008-09-18
申请号：US11685422
申请日：2007-03-13
申请人： Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
发明人： Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
IPC分类号： G06F15/76
CPC分类号： G06F9/5061 , G06F9/3885 , G06F9/3891 , G06F9/3897
摘要： A configurable microprocessor that handles low computing-intensive workloads by partitioning a single processor core into two smaller corelets. The process partitions resources of a single microprocessor core to form a plurality of corelets and assigns a set of the partitioned resources to each corelet. Each set of partitioned resources is dedicated to one corelet to allow each corelet to function independently of other corelets in the plurality of corelets. The process also combines a plurality of corelets into a single microprocessor core by combining corelet resources to form a single microprocessor core. The combined resources feed the single microprocessor core.
摘要翻译：一个可配置的微处理器，通过将单个处理器内核分成两个较小的核心处理器来处理低计算密集型工作负载。该过程分割单个微处理器核心的资源以形成多个核心小区，并将一组分割的资源分配给每个小核。每组分区资源专用于一个corelet，以允许每个corelet独立于多个corelet中的其他corelet进行运行。该过程还通过组合核心资源来形成单个微处理器核心，将多个核心组合成单个微处理器核心。组合的资源馈送单个微处理器内核。

8. 发明授权

US08086826B2 Dependency tracking for enabling successive processor instructions to issue 有权
标题翻译：用于启用连续处理器指令发布的依赖性跟踪
公开(公告)号：US08086826B2
公开(公告)日：2011-12-27
申请号：US12409934
申请日：2009-03-24
申请人： Mary Douglass Brown , William Elton Burky , Dung Quoc Nguyen , Balaram Sinharoy
发明人： Mary Douglass Brown , William Elton Burky , Dung Quoc Nguyen , Balaram Sinharoy
IPC分类号： G06F9/38 , G06F9/52
CPC分类号： G06F9/3814 , G06F9/3838
摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.
摘要翻译：信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。

9. 发明授权

US07631308B2 Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
标题翻译：线程优先级方法，用于确保同时多线程微处理器的处理公平性
公开(公告)号：US07631308B2
公开(公告)日：2009-12-08
申请号：US11055850
申请日：2005-02-11
申请人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
发明人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4818 , G06F9/485
摘要： A method is disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread.
摘要翻译：在数据处理系统中公开了一种用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性的方法。在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。

10. 发明申请

US20080294884A1 Thread Priority Method for Ensuring Processing Fairness in Simultaneous Multi-Threading Microprocessors 失效
标题翻译：用于确保同时多线程微处理器处理公平性的线程优先级方法
公开(公告)号：US20080294884A1
公开(公告)日：2008-11-27
申请号：US12129876
申请日：2008-05-30
申请人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
发明人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4818 , G06F9/485
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.
摘要翻译：在数据处理系统中公开了一种方法，装置和计算机程序产品，用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性。在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

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