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1. 发明授权

US07404019B2 Method and apparatus for endianness control in a data processing system 有权
标题翻译：数据处理系统中字节序控制的方法和装置
公开(公告)号：US07404019B2
公开(公告)日：2008-07-22
申请号：US10857208
申请日：2004-05-26
申请人： William C. Moyer , Michael D. Fitzsimmons
发明人： William C. Moyer , Michael D. Fitzsimmons
IPC分类号： G06F13/12 , G06F3/00 , G06F13/00
CPC分类号： G06F13/4013 , G06F21/85 , G06F2221/2113 , G06F2221/2141
摘要： A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect the endianness order of the information transferred during the access. In one embodiment, the first endianness control overrides a default endianness corresponding to the access. The default endianness may be provided by a master endianness control corresponding to a master requesting the current access. A data processing system includes a first bus master, first and second peripherals, first endianness control corresponding to the first peripheral and second endianness control corresponding to the second peripheral, and control circuitry which uses the first endianness control to control endianness for an access between the first bus master and the first peripheral. In one embodiment, the data processing system may include multiple masters.
摘要翻译：一种用于在数据处理系统中提供字节序控制的方法包括发起访问外围设备的访问，提供与外设相对应的第一字节序列控制，并使用字节序控制来完成访问，以影响在该时间间隔期间传送的信息的字节顺序访问。在一个实施例中，第一字节序列控制覆盖对应于访问的默认字节顺序。默认字节顺序可以由对应于请求当前访问的主机的主字节顺序控制来提供。数据处理系统包括第一总线主机，第一和第二外围设备，对应于与第二外围设备相对应的第一外设和第二终端控制的第一字节序列控制;以及控制电路，其使用第一字节序列控制来控制字节顺序第一个总线主人和第一个外围设备。在一个实施例中，数据处理系统可以包括多个主器件。

2. 发明授权

US07099973B2 Method and system of bus master arbitration 有权
标题翻译：总线主控仲裁的方法和系统
公开(公告)号：US07099973B2
公开(公告)日：2006-08-29
申请号：US10402165
申请日：2003-03-26
申请人： William C. Moyer , Michael D. Fitzsimmons , Brett W. Murdock
发明人： William C. Moyer , Michael D. Fitzsimmons , Brett W. Murdock
IPC分类号： G06F13/36 , G06F3/00
CPC分类号： G06F13/364
摘要： A system (100) having a plurality of bus masters (111–113) coupled to an arbiter (150) is disclosed. An arbiter (150) is coupled to a first storage location (151) and a second storage location (152), where the first and second storage locations store bus master parking information for a system bus (141). The arbiter (150) receives a parking context indicator (131) that is used to select one of the first and second storage locations (151, 152) to provide bus master parking information to the arbiter (150).
摘要翻译：公开了具有耦合到仲裁器（150）的多个总线主机（111-113）的系统（100）。仲裁器（150）耦合到第一存储位置（151）和第二存储位置（152），其中第一和第二存储位置存储用于系统总线（141）的总线主站停车信息。仲裁器（150）接收用于选择第一和第二存储位置（151,152）之一以便向仲裁器（150）提供总线主机停车信息的停车上下文指示器（131）。

3. 发明授权

US07500152B2 Apparatus and method for time ordering events in a system having multiple time domains 失效
标题翻译：用于具有多个时域的系统中的时间排序事件的装置和方法
公开(公告)号：US07500152B2
公开(公告)日：2009-03-03
申请号：US10728398
申请日：2003-12-05
申请人： William C. Moyer , Richard G. Collins , Michael D. Fitzsimmons , Jason T. Nearing
发明人： William C. Moyer , Richard G. Collins , Michael D. Fitzsimmons , Jason T. Nearing
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3632 , G06F11/3648
摘要： A system and method time orders events that occur in various portions of the system (10) where different time domains (12, 22, 32) exist. Timestamping circuitry (e.g. 40) is provided in each of a plurality of functional circuits or modules (14, 24, 34). The timestamping circuitry provides a message that indicates a point in time when a predetermined event occurs. An interface module (70) is coupled to each of the plurality of functional circuits (14, 24, 34). The interface module (70) provides control information to the plurality of functional circuits (14, 24, 34) to indicate at least one operating condition that triggers the predetermined event, and to optionally specify a message format. The interface module (70) provides a timestamping message from one, several or all time domains at a common interface port (90).
摘要翻译：系统和方法时间顺序发生在存在不同时域（12,22,32）的系统（10）的各个部分中的事件。在多个功能电路或模块（14,24,34）中的每一个中提供时间戳电路（例如40）。时间戳电路提供指示发生预定事件的时间点的消息。接口模块（70）耦合到多个功能电路（14,24,34）中的每一个。接口模块（70）向多个功能电路（14,24,34）提供控制信息以指示触发预定事件的至少一个操作条件，并且可选地指定消息格式。接口模块（70）在公共接口端口（90）处提供来自一个，几个或所有时域的时间戳消息。

4. 发明授权

US07278062B2 Method and apparatus for responding to access errors in a data processing system 有权
标题翻译：用于在数据处理系统中响应访问错误的方法和装置
公开(公告)号：US07278062B2
公开(公告)日：2007-10-02
申请号：US10339022
申请日：2003-01-09
申请人： William C. Moyer , Michael D. Fitzsimmons , Brian M. Millar , John J. Vaglica
发明人： William C. Moyer , Michael D. Fitzsimmons , Brian M. Millar , John J. Vaglica
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G06F11/0745 , G06F11/0751 , G06F11/0793
摘要： In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.
摘要翻译：在一个实施例中，数据处理系统（10）具有耦合到总线的处理器（14），其中数据处理系统（10）包括访问错误检测电路（26）和访问错误响应电路（12），每个耦合到公共汽车（58,60）。访问错误检测电路检测数据处理系统中的访问错误。当检测到访问错误时，访问错误响应电路以预定值启动总线上的现有值的替换，并且当已经检测到访问错误时，继续以预定值替换总线上的现有值，并且持续模式指示器已被断言。预定值可以对应于预定指令值（74）或预定数据值（76）。在一个实施例中，可以根据数据处理系统的当前操作模式使用预定值的不同值。

5. 发明授权

US07155618B2 Low power system and method for a data processing system 有权
公开(公告)号：US07155618B2
公开(公告)日：2006-12-26
申请号：US10094053
申请日：2002-03-08
申请人： William C. Moyer , Brian M. Millar , Michael D. Fitzsimmons
发明人： William C. Moyer , Brian M. Millar , Michael D. Fitzsimmons
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3237 , G06F1/3203 , Y02D10/128 , Y02D50/20
摘要： Systems and methods are discussed to identify a recoverable state in a low power device. A low power device having an arbiter to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller within the low power device provides a request to the bus arbiter to initiate a low power mode. The bus arbiter stops granting bus requests to the bus masters and identifies when the system bus has processed all current bus accesses. When the system bus is idle, the bus arbiter returns a bus grant signal to the low power controller. Clocks associated with the bus masters are disabled to suspend the bus arbiters and allow less power to be consumed by the low power device.

6. 发明授权

US07353311B2 Method of accessing information and system therefor 有权
标题翻译：访问信息的方法及其系统
公开(公告)号：US07353311B2
公开(公告)日：2008-04-01
申请号：US11142148
申请日：2005-06-01
申请人： Brett W. Murdock , William C. Moyer , Michael D. Fitzsimmons
发明人： Brett W. Murdock , William C. Moyer , Michael D. Fitzsimmons
IPC分类号： G06F12/00 , G06F13/14 , G06F13/38
CPC分类号： G06F13/4022
摘要： A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority amongst the transactions, or use to index storage locations that indicate priority values. The transaction identifiers can be selected to be associated with a transaction by the requesting device or other priority determination module based upon predefined criteria.
摘要翻译：公开了一种方法，其中基于与每个交易相关联的交易标识符来确定能够在公共时间处理的交易中的优先级。事务标识符可以直接指示事务之间的优先级，或用于索引指示优先级值的存储位置。可以基于预定义的标准，将请求设备或其他优先级确定模块的交易标识符选择为与交易相关联。

7. 发明授权

US07277972B2 Data processing system with peripheral access protection and method therefor 有权
标题翻译：具有外设访问保护的数据处理系统及其方法
公开(公告)号：US07277972B2
公开(公告)日：2007-10-02
申请号：US10094082
申请日：2002-03-08
申请人： William C. Moyer , Michael D. Fitzsimmons
发明人： William C. Moyer , Michael D. Fitzsimmons
IPC分类号： G06F13/14 , G06F12/14
CPC分类号： G06F21/85
摘要： One embodiment of the present invention provides a flexible peripheral access protection mechanism within a data processing system (10) in order to obtain a more secure operating environment. For example, the data processing system may include a combination of secure (12) and unsecure bus masters (14, 15) needing to access shared peripherals (22, 24). One embodiment allows for the dynamic update by a secure bus master (12) of access permissions corresponding to each unsecure bus master for each peripheral. A secure bus master is therefore able to establish which unsecure bus masters have permission to access which peripheral in order to protect the data processing system from corruption due to errant or hostile software running on unsecure bus masters. Through the use of a bus master identifier (36), access to the requested peripheral is either allowed or denied based on the permissions established by the secure bus master.
摘要翻译：本发明的一个实施例提供了数据处理系统（10）内的灵活的周边访问保护机制，以便获得更安全的操作环境。例如，数据处理系统可以包括需要访问共享外围设备（22,24）的安全（12）和不安全总线主控器（14,15）的组合。一个实施例允许由安全总线主机（12）对与每个外设的每个不安全总线主机相对应的访问许可的动态更新。因此，安全总线主机能够确定哪些不安全的总线主人有权访问哪些外围设备，以便保护数据处理系统免受由于不安全的总线主机上运行的错误或恶意软件的损坏。通过使用总线主机标识符（36），可以根据安全总线主机建立的许可来允许或拒绝对请求的外设的访问。

8. 发明授权

US07266848B2 Integrated circuit security and method therefor 有权
标题翻译：集成电路安全及其方法
公开(公告)号：US07266848B2
公开(公告)日：2007-09-04
申请号：US10100462
申请日：2002-03-18
申请人： William C. Moyer , Michael D. Fitzsimmons
发明人： William C. Moyer , Michael D. Fitzsimmons
IPC分类号： G06F21/00
CPC分类号： G01R31/31719
摘要： The invention relates to an integrated circuit (IC), and more particularly to security to protect an IC (10) against unauthorized accesses. In one embodiment, an identifier is provided external to IC 10. A corresponding input IC security key (52) is then provided to IC 10 and compared to a stored IC security key (30). If the input IC security key (52) and the stored IC security key (30) do not match, access to protected functional circuitry (12) is prohibited. The present invention may use any debug interface, including standard debug interfaces using the JTAG 1149.1 interface defined by the IEEE.
摘要翻译：本发明涉及集成电路（IC），并且更具体地涉及用于保护IC（10）防止未授权访问的安全性。在一个实施例中，在IC 10外部提供标识符。然后将对应的输入IC安全密钥（52）提供给IC 10，并与存储的IC安全密钥（30）进行比较。如果输入IC安全密钥（52）和存储的IC安全密钥（30）不匹配，则禁止对受保护功能电路（12）的访问。本发明可以使用任何调试接口，包括使用IEEE定义的JTAG 1149.1接口的标准调试接口。

9. 发明授权

US06378022B1 Method and apparatus for processing interruptible, multi-cycle instructions 有权
标题翻译：用于处理可中断，多周期指令的方法和装置
公开(公告)号：US06378022B1
公开(公告)日：2002-04-23
申请号：US09335105
申请日：1999-06-17
申请人： William C. Moyer , Jeffrey W. Scott , Michael D. Fitzsimmons
发明人： William C. Moyer , Jeffrey W. Scott , Michael D. Fitzsimmons
IPC分类号： G06F1324
CPC分类号： G06F9/3836 , G06F9/3001 , G06F9/30065 , G06F9/3859 , G06F9/3869 , G06F13/24
摘要： A method and apparatus for processing multi-cycle instructions. In one embodiment, the method includes beginning execution of a multi-cycle instruction by the processing device, and, during execution of the multi-cycle instruction, comparing a threshold value to a count value that indicates a number of remaining cycles before completion of the multi-cycle instruction. In one embodiment, the apparatus includes a processing unit. The processing unit includes an interrupt control module that has an interrupt request signal input and a second input to receive a multi-cycle instruction interrupt signal. The multi-cycle instruction interrupt signal is to indicate an interruptible interval when an interrupt of a multi-cycle instruction is permitted prior to completion of the multi-cycle instruction.
摘要翻译：一种用于处理多周期指令的方法和装置。在一个实施例中，该方法包括由处理装置开始执行多周期指令，并且在执行多周期指令期间，将阈值与表示完成之前的剩余周期数的计数值进行比较多周期指令在一个实施例中，该装置包括处理单元。处理单元包括具有中断请求信号输入的中断控制模块和用于接收多周期指令中断信号的第二输入。多周期指令中断信号是指示在多周期指令完成之前允许多周期指令的中断的可中断间隔。

10. 发明授权

US07185121B2 Method of accessing memory via multiple slave ports 有权
标题翻译：通过多个从端口访问存储器的方法
公开(公告)号：US07185121B2
公开(公告)日：2007-02-27
申请号：US11203935
申请日：2005-08-15
申请人： Michael D. Fitzsimmons , William C. Moyer , Brett W. Murdock
发明人： Michael D. Fitzsimmons , William C. Moyer , Brett W. Murdock
IPC分类号： G06F13/28
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port control circuitry (48), configuration registers (46) and slave port arbiter logic (34, 36, 38, 40, 42 and 44) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.
摘要翻译：交叉开关（12）仲裁用于从多个总线主机（14,16,18,20和22）到具有重叠地址范围的多个寻址从端口（3和4）的访问。在一种形式中，地址范围是相同的地址范围。当所有寻址端口都忙时，交叉开关（12）使用共享从端口控制电路（48），配置寄存器（46）和从端口仲裁器逻辑（34,36,38,40,42和44）仲裁访问。确定新的访问请求是否比现有访问的优先级更高或更低。基于对包括所请求的数据跳动的数量以及等待状态信息的各种因素的预测，首先将确定某个多个访问中的哪一个将首先完成，从而确定何时引导新的访问请求。在一种模式中，动态地确定等待状态信息。

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