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1. 发明申请

US20220233943A1 Interactive Pitching Training Apparatus and System 有权
公开(公告)号：US20220233943A1
公开(公告)日：2022-07-28
申请号：US17155137
申请日：2021-01-22
申请人： William A. Brant , Robert T. Peacock
发明人： William A. Brant , Robert T. Peacock
IPC分类号： A63B71/06 , A63B69/00 , A63B63/00 , A63B24/00
摘要： A pitching interactive training system having of a mat against which a ball is thrown. The mat has an embedded electronic display of a strike zone broken down into subsidiary “zones” and an exterior perimeter of “zones” just outside the strike zone. The embedded sensors and electronics when hit with a pitch register a point value on a scoreboard. Assignment of values may be adjusted for each pitch by remote control for each batter depending upon the game situation. The electronic scoreboard registers whether a ball or a strike and values for each pitch and maintains a total score with a reset for each new batter. The embedded electronics and scoreboard are powered by battery and rechargeable via an attached electric cord plugged into a standard electrical outlet. An optional radar gun records the speed of each pitch. An optional high speed sports camera attached to the system allows measurement of pitch spin rotations, pitch release point, and captures the entire pitch delivery process for replay to aid coaching and visualizing pitch command.

2. 发明授权

US5799200A Power failure responsive apparatus and method having a shadow dram, a flash ROM, an auxiliary battery, and a controller 失效
标题翻译：具有阴影的电源故障响应装置和方法，闪存ROM，辅助电池和控制器
公开(公告)号：US5799200A
公开(公告)日：1998-08-25
申请号：US536519
申请日：1995-09-28
申请人： William A. Brant , Michael E. Nielson , Edde Tin-Shek Tang
发明人： William A. Brant , Michael E. Nielson , Edde Tin-Shek Tang
IPC分类号： G06F1/30 , G06F11/14 , G06F1/00
CPC分类号： G06F1/30 , G06F11/1441
摘要： Data in a system having dynamic random access memories (DRAM's) is preserved despite loss of the primary source of electrical power to that system. A Flash RAM and a small auxiliary power source are employed by a controller independent of the system to transfer the DRAM contents to the Flash RAM immediately upon loss of primary system power. The data is also automatically returned to the DRAM after return of primary power with special data signals or sequences being utilized in a multiple controller environment so as to award the complete data recovery function to the first controller to demand attention.
摘要翻译：尽管丢失了该系统的主要电源，仍保留了具有动态随机存取存储器（DRAM）的系统中的数据。闪存RAM和小型辅助电源被独立于系统的控制器采用，以在主系统电源丢失时立即将DRAM内容传送到闪存RAM。在多次控制器环境中使用特殊数据信号或序列返回主电源之后，数据也自动返回到DRAM，以便将完整的数据恢复功能授予第一控制器以要求注意。

3. 发明授权

US5617530A Storage device array architecture with copyback cache 失效
标题翻译：存储设备阵列架构与副本缓存
公开(公告)号：US5617530A
公开(公告)日：1997-04-01
申请号：US579545
申请日：1995-12-27
申请人： David C. Stallmo , William A. Brant
发明人： David C. Stallmo , William A. Brant
IPC分类号： G06F3/06 , G06F11/10 , G06F11/14 , G06F11/20 , G06F12/08 , G06F12/16 , G11B20/18
CPC分类号： G06F11/1666 , G06F11/1076 , G06F11/1435 , G06F11/2087 , G06F11/2094 , G06F12/0804 , G11B20/1833 , G06F11/1441 , G06F11/20 , G06F11/2089 , G06F12/0866 , G06F2211/1019 , G06F2211/1059
摘要： A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, Read-Modify-Write operations are performed during idle time. In a second embodiment of the invention, normal Read-Modify-Write operation by the RAID system controller continue use Write data in the controller's buffer memory. In a third embodiment, at least two controllers, each associated with one copyback cache storage unit, copy Write data from controller buffers to the associated copyback cache storage unit. If a copyback cache storage unit fails, more than one controller share a single copyback storage unit. In a fourth embodiment, Write data is copied from a controller buffer to a reserved area of each storage unit comprising the array.
摘要翻译：使用用于临时存储的副本缓存存储单元的容错存储设备阵列。当RAID系统发生写入时，数据将立即写入拷贝缓存存储单元中的第一个可用位置。完成写回到高速缓存存储单元后，主机CPU立即通知写入成功。此后，可以继续CPU的进一步存储单元访问，而不用等待刚刚写入的数据的纠错块更新。在本发明的第一实施例中，在空闲时间期间执行读 - 修改 - 写操作。在本发明的第二实施例中，RAID系统控制器的正常读 - 修改 - 写操作继续使用控制器缓冲存储器中的写数据。在第三实施例中，每个与一个拷贝高速缓存存储单元相关联的至少两个控制器将从控制器缓冲器写入数据复制到相关联的副本缓存存储单元。如果副本缓存存储单元出现故障，则多个控制器共享单个副本存储单元。在第四实施例中，将写入数据从控制器缓冲器复制到包括阵列的每个存储单元的保留区域。

4. 发明授权

US5235601A On-line restoration of redundancy information in a redundant array system 失效
标题翻译：在冗余阵列系统中在线恢复冗余信息
公开(公告)号：US5235601A
公开(公告)日：1993-08-10
申请号：US632182
申请日：1990-12-21
申请人： David C. Stallmo , William A. Brant , David Gordon
发明人： David C. Stallmo , William A. Brant , David Gordon
IPC分类号： G06F3/06 , G06F11/08 , G06F11/10 , G06F11/14 , G06F12/00 , G06F12/16
CPC分类号： G06F11/1076 , G06F11/1435
摘要： A method for on-line restoration of redundancy information in a redundant array storage system. The invention provides alternative methods of restoring valid data to a storage unit after a Write failure caused by a temporary storage unit fault. In the first preferred method, a valid redundancy block is generated for the corresponding data blocks on all storage units. Resubmitting the interrupted Write operation causes the old (and potentially corrupted) data block to be "subtracted" out of the re-computed redundancy block. The uncorrupted new data block is written over the old data block, and is "added" into the recomputed redundancy block to create a new, corrected redundancy block. The new, corrected redundancy block is written to the appropriate storage unit. In the second preferred method, a new redundancy block is generated from all valid data blocks and the new data block. The new redundancy block and the new data block are then written to the appropriate storage units. In both cases, the entire method is done on-line, with insignificant interruption of normal operation of the redundant array system, and without requiring added processing during normal operation.

5. 发明授权

US5831393A Flexible parity generation circuit 失效
标题翻译：灵活的奇偶生成电路
公开(公告)号：US5831393A
公开(公告)日：1998-11-03
申请号：US832050
申请日：1997-04-02
申请人： Gerald Lee Hohenstein , Michael E. Nielson , Tin S. Tang , Richard D. Carmichael , William A. Brant
发明人： Gerald Lee Hohenstein , Michael E. Nielson , Tin S. Tang , Richard D. Carmichael , William A. Brant
IPC分类号： G06F11/10 , G11B20/18 , G06F11/00
CPC分类号： G06F11/1076 , G11B20/1833 , G06F2211/1054
摘要： A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.
摘要翻译：具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。例如，这样的系统可以具有用于处理两组数据的两个通道。奇偶产生技术采用切换装置来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。对于某些系统应用，可能希望将RAM用作大型统一的FIFO。因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。

6. 发明授权

US5675726A Flexible parity generation circuit 失效
标题翻译：灵活的奇偶生成电路
公开(公告)号：US5675726A
公开(公告)日：1997-10-07
申请号：US555331
申请日：1995-11-08
申请人： Gerald Lee Hohenstein , Michael E. Nielson , Tin S. Tang , Richard D. Carmichael , William A. Brant
发明人： Gerald Lee Hohenstein , Michael E. Nielson , Tin S. Tang , Richard D. Carmichael , William A. Brant
IPC分类号： G06F11/10 , G11B20/18 , G06F11/00
CPC分类号： G06F11/1076 , G11B20/1833 , G06F2211/1054
摘要： A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.
摘要翻译：具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。例如，这样的系统可以具有用于处理两组数据的两个通道。奇偶产生技术采用切换装置来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。对于某些系统应用，可能希望将RAM用作大型统一的FIFO。因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。

7. 发明授权

US5613059A On-line restoration of redundancy information in a redundant array system 失效
标题翻译：在冗余阵列系统中冗余信息的在线恢复
公开(公告)号：US5613059A
公开(公告)日：1997-03-18
申请号：US349766
申请日：1994-12-01
申请人： David C. Stallmo , William A. Brant , David Gordon
发明人： David C. Stallmo , William A. Brant , David Gordon
IPC分类号： G06F3/06 , G06F11/08 , G06F11/10 , G06F11/14 , G06F12/00 , G06F12/16 , G06F11/34
CPC分类号： G06F11/1076 , G06F11/1435
摘要： A method for on-line restoration of redundancy information in a redundant array storage system. The invention provides alternative methods of restoring valid data to a storage unit after a Write failure caused by a temporary storage unit fault. In the first preferred method, a valid redundancy block is generated for the corresponding data blocks on all storage units. Resubmitting the interrupted Write operation causes the old (and potentially corrupted) data block to be "subtracted" out of the re-computed redundancy block. The uncorrupted new data block is written over the old data block, and is "added" into the re-computed redundancy block to create a new, corrected redundancy block. The new, corrected redundancy block is written to the appropriate storage unit. In the second preferred method, a new redundancy block is generated from all valid data blocks and the new data block. The new redundancy block and the new data block are then written to the appropriate storage units. In both cases, the entire method is done on-line, with insignificant interruption of normal operation of the redundant array system, and without requiring added processing during normal operation.
摘要翻译：一种冗余阵列存储系统中冗余信息的在线恢复方法。本发明提供了在由临时存储单元故障引起的写入故障之后将有效数据恢复到存储单元的替代方法。在第一优选方法中，为所有存储单元上的相应数据块生成有效的冗余块。重新提交中断的写入操作会导致旧的（可能被破坏的）数据块从重新计算的冗余块中“减去”。未破坏的新数据块被写入旧的数据块，并被“添加”到重新计算的冗余块中以创建新的校正的冗余块。新的校正冗余块被写入适当的存储单元。在第二优选方法中，从所有有效数据块和新数据块生成新的冗余块。然后将新的冗余块和新的数据块写入适当的存储单元。在这两种情况下，整个方法都是在线完成的，冗余阵列系统的正常运行中断，并且在正常运行期间不需要额外的处理。

8. 发明授权

US5526482A Storage device array architecture with copyback cache 失效
公开(公告)号：US5526482A
公开(公告)日：1996-06-11
申请号：US112791
申请日：1993-08-26
申请人： David C. Stallmo , William A. Brant
发明人： David C. Stallmo , William A. Brant
IPC分类号： G06F3/06 , G06F11/10 , G06F11/14 , G06F11/20 , G06F12/08 , G06F12/16 , G11B20/18 , G06F11/00
CPC分类号： G06F11/1666 , G06F11/1076 , G06F11/1435 , G06F11/2087 , G06F11/2094 , G06F12/0804 , G11B20/1833 , G06F11/1441 , G06F11/20 , G06F11/2089 , G06F12/0866 , G06F2211/1019 , G06F2211/1059
摘要： A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, Read-Modify-Write operations are performed during idle time. In a second embodiment of the invention, normal Read-Modify-Write operation by the RAID system controller continue use Write data in the controller's buffer memory. In a third embodiment, at least two controllers, each associated with one copyback cache storage unit, copy Write data from controller buffers to the associated copyback cache storage unit. If a copyback cache storage unit fails, more than one controller share a single copyback storage unit. In a fourth embodiment, Write data is copied from a controller buffer to a reserved area of each storage unit comprising the array.

9. 发明授权

US5058885A Warmup aid ball 失效
标题翻译：预热辅助球
公开(公告)号：US5058885A
公开(公告)日：1991-10-22
申请号：US549908
申请日：1990-07-09
申请人： William A. Brant
发明人： William A. Brant
IPC分类号： A63B21/06 , A63B23/12
CPC分类号： A63B21/0603 , A63B21/4035 , A63B21/4043 , A63B23/03508 , A63B23/12 , A63B21/4019 , A63B23/1209
摘要： A warmup aid ball having an outer shell, an inner weighted core, and a multiplicity of contiguous finger retaining loops in a side-by-side lateral arrangement. Each separate loop is attached to the outer shell at a base portion. The base portions of the end loops are arcuated at the area where the base attaches to the outer shell of the ball to accommodate those digits not retained in a loop in a position to eliminate irritation and discomfort. Each loop is slightly displaceable, side-to-side to facilitate varying hand and finger sizes.
摘要翻译：具有外壳，内加重芯和多个连续的手指保持环并列排列的预热辅助球。每个单独的环在基部附接到外壳。端部环的基部在基部附接到球的外壳的区域处弧形化，以容纳不保留在环中的位置，以消除刺激和不适。每个环路都可以稍微移位，从侧到左，以方便手和手指尺寸的变化。

10. 发明授权

US06763398B2 Modular RAID controller 有权
标题翻译：模块化RAID控制器
公开(公告)号：US06763398B2
公开(公告)日：2004-07-13
申请号：US09941469
申请日：2001-08-29
申请人： William A. Brant , Randall F. Horning
发明人： William A. Brant , Randall F. Horning
IPC分类号： G06F300
CPC分类号： G06F3/0658 , G06F3/0626 , G06F3/0689
摘要： A storage controller for redundant arrays of independent disks (RAID) comprises a daughter card containing a standardized controller core, which is mated to one of a number of customizable controller interface cards. The controller core card includes high performance elements such as a processor, cache memory, CRC circuitry, a host port, and a storage port. All operational communication with non-core components occurs via the host port and the storage port through the controller interface card. The controller core card monitors and configures communications between the host and the storage array. Each controller interface card is populated with components and connectors particular to the respective application or RAID system. The size and layout of the controller interface card may also be customized to the particular application. Sharing the same controller core card among various RAID controllers lowers the cost and time-to-market for customized RAID systems.
摘要翻译：用于独立磁盘（RAID）的冗余阵列的存储控制器包括含有标准化控制器核心的子卡，其与多个可定制的控制器接口卡之一配合。控制器核心卡包括诸如处理器，高速缓冲存储器，CRC电路，主机端口和存储端口的高性能元件。与非核心组件的所有操作通信通过主机端口和存储端口通过控制器接口卡进行。控制器核心卡监视和配置主机与存储阵列之间的通信。每个控制器接口卡都填充有相应应用程序或RAID系统特有的组件和连接器。控制器接口卡的尺寸和布局也可以根据具体应用进行定制。在各种RAID控制器之间共享相同的控制器核心卡降低了定制RAID系统的成本和上市时间。

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