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1. 发明授权

US08410541B2 CMOSFET device with controlled threshold voltage characteristics and method of fabricating the same 有权
标题翻译：具有受控阈值电压特性的CMOSFET器件及其制造方法
公开(公告)号：US08410541B2
公开(公告)日：2013-04-02
申请号：US12935364
申请日：2010-06-24
申请人： Wenwu Wang , Huilong Zhu , Shijie Chen , Dapeng Chen
发明人： Wenwu Wang , Huilong Zhu , Shijie Chen , Dapeng Chen
IPC分类号： H01L29/792
CPC分类号： H01L29/513 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO2, is interposed inside high-k gate dielectric layers of the CMOSFET device, and the threshold voltage is adjusted by means of the interface dipoles formed by the cap layer inside the high-k gate dielectric layers. According to the present invention, it is possible to effectively optimize the threshold voltage of the CMOSFET device without significantly increasing EOT thereof.
摘要翻译：提供了具有通过接口偶极子控制的阈值电压的CMOSFET器件及其制造方法。覆盖层，例如非常薄的多晶硅，非晶硅或SiO 2层被插入在CMOSFET器件的高k栅极电介质层的内部，并且阈值电压通过由盖层在高k栅介质层内。根据本发明，可以有效地优化CMOSFET器件的阈值电压而不显着增加其EOT。

2. 发明申请

US20110169097A1 CMOSFET DEVICE WITH CONTROLLED THRESHOLD VOLTAGE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有受控阈值电压的CMOSFET器件及其制造方法
公开(公告)号：US20110169097A1
公开(公告)日：2011-07-14
申请号：US12937444
申请日：2010-06-24
申请人： Wenwu Wang , Huilong Zhu , Shijie Chen , Dapeng Chen
发明人： Wenwu Wang , Huilong Zhu , Shijie Chen , Dapeng Chen
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823857 , H01L27/092 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; an interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer. According to to the present invention, the very thin metal layers are deposited between the high-k gate dielectric layers for NMOS and PMOS devices respectively, such that a flat band voltage of the device is adjusted by means of positive or negative charges generated by the metal layers inside the high-k gate dielectric layers, and thus the threshold voltage of the device is controlled. Thus, it is possible not only to is enhance interface dipoles between the high-k dielectric layers and the SiO2 interface layer, but also to well control types and amounts of fixed charges inside the high-k gate dielectric layers, so as to effectively control the threshold voltage of the device.
摘要翻译：提供了具有通过其栅极堆叠配置控制的阈值电压的CMOSFET器件及其制造方法。 CMOSFET器件包括：半导体衬底; 在硅衬底上生长的界面层; 沉积在界面层上的第一高k栅介质层; 沉积在第一高k栅极电介质层上的非常薄的金属层; 沉积在金属层上的第二高k栅介质层; 以及沉积在第二高k栅极电介质层上的栅电极层。根据本发明，非常薄的金属层分别沉积在用于NMOS和PMOS器件的高k栅极电介质层之间，使得器件的平带电压通过由金属层在高k栅极电介质层内，因此控制器件的阈值电压。因此，不仅可以增强高k电介质层和SiO 2界面层之间的界面偶极子，而且可以很好地控制高k栅极电介质层内的固定电荷的类型和量，以有效地控制器件的阈值电压。

3. 发明授权

US08410555B2 CMOSFET device with controlled threshold voltage and method of fabricating the same 有权
标题翻译：具有受控阈值电压的CMOSFET器件及其制造方法
公开(公告)号：US08410555B2
公开(公告)日：2013-04-02
申请号：US12937444
申请日：2010-06-24
申请人： Wenwu Wang , Huilong Zhu , Shijie Chen , Dapeng Chen
发明人： Wenwu Wang , Huilong Zhu , Shijie Chen , Dapeng Chen
IPC分类号： H01L27/12
CPC分类号： H01L21/823857 , H01L27/092 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; am interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the very thin metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer.
摘要翻译：提供了具有通过其栅极堆叠配置控制的阈值电压的CMOSFET器件及其制造方法。 CMOSFET器件包括：半导体衬底; 在硅衬底上生长的界面层; 沉积在界面层上的第一高k栅介质层; 沉积在第一高k栅极电介质层上的非常薄的金属层; 沉积在非常薄的金属层上的第二高k栅介质层; 以及沉积在第二高k栅极电介质层上的栅电极层。

4. 发明申请

US20120104506A1 CMOSFET DEVICE WITH CONTROLLED THRESHOLD VOLTAGE CHARACTERISTICS AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有受控阈值电压特性的CMOSFET器件及其制造方法
公开(公告)号：US20120104506A1
公开(公告)日：2012-05-03
申请号：US12935364
申请日：2010-06-24
申请人： Wenwu Wang , Huilong Zhu , Shijie Chen , Depeng Chen
发明人： Wenwu Wang , Huilong Zhu , Shijie Chen , Depeng Chen
IPC分类号： H01L27/092 , H01L21/20
CPC分类号： H01L29/513 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO2, is interposed inside high-k gate dielectric layers of the CMOSFET device, and the threshold voltage is adjusted by means of the interface dipoles formed by the cap layer inside the high-k gate dielectric layers. According to the present invention, it is possible to effectively optimize the threshold voltage of the CMOSFET device without significantly increasing EOT thereof.
摘要翻译：提供了具有通过接口偶极子控制的阈值电压的CMOSFET器件及其制造方法。覆盖层，例如非常薄的多晶硅，非晶硅或SiO 2层被插入在CMOSFET器件的高k栅极电介质层的内部，并且阈值电压通过由盖层在高k栅介质层内。根据本发明，可以有效地优化CMOSFET器件的阈值电压而不显着增加其EOT。

5. 发明授权

US08507991B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08507991B2
公开(公告)日：2013-08-13
申请号：US13517893
申请日：2012-06-14
申请人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
发明人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
IPC分类号： H01L29/76 , H01L29/94 , H01L27/108 , H01L31/119 , H01L31/062
CPC分类号： H01L21/823857 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment.
摘要翻译：提供半导体器件。通过在通过替换栅极工艺制造CMOS晶体管中的快速退火，通过单原子结构的超薄高k电介质材料形成包含衬底元件的多组分高k界面层，并且在其上形成具有较高介电常数的高k栅极电介质层和金属栅极层。有效地减少器件的EOT，并且通过在高温处理下的优化的高k界面层有效地防止了高k栅介质层中的原子从其上层的扩散。

6. 发明申请

US20120261761A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120261761A1
公开(公告)日：2012-10-18
申请号：US13517893
申请日：2012-06-14
申请人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
发明人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
IPC分类号： H01L27/088
CPC分类号： H01L21/823857 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment.
摘要翻译：提供半导体器件。通过在通过替换栅极工艺制造CMOS晶体管中的快速退火，通过单原子结构的超薄高k电介质材料形成包含衬底元件的多组分高k界面层，并且在其上形成具有较高介电常数的高k栅极电介质层和金属栅极层。有效地减少器件的EOT，并且通过在高温处理下的优化的高k界面层有效地防止了高k栅介质层中的原子从其上层的扩散。

7. 发明授权

US08222099B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08222099B2
公开(公告)日：2012-07-17
申请号：US13063564
申请日：2010-06-24
申请人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
发明人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
IPC分类号： H01L27/088
CPC分类号： H01L21/823857 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility. Furthermore, the present invention may further alleviate the problem of high interface state and interface roughness caused by direct contact of the high-k gate dielectric layer with high dielectric constant and the substrate, and thus the overall performance of the device is effectively enhanced.
摘要翻译：提供半导体器件及其制造方法。通过在通过替换栅极工艺制造CMOS晶体管中的快速退火，通过单层原子结构的超薄高k介电材料形成包含衬底元件的多组分高k界面层，并且在其上形成具有较高介电常数的高k栅极电介质层和金属栅极层。有效地减少器件的EOT，并且通过在高温处理下的优化的高k界面层有效地防止了高k栅介质层中的原子从其上层的扩散。因此，本发明还可以避免界面层的生长和载流子迁移率的劣化。此外，本发明还可以进一步减轻高介电常数和高介电常数直接接触引起的高界面态和界面粗糙度问题，从而有效提高器件的整体性能。

8. 发明授权

US08563415B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08563415B2
公开(公告)日：2013-10-22
申请号：US13061879
申请日：2010-06-24
申请人： Wenwu Wang , Shijie Chen , Xiaolei Wang , Kai Han , Dapeng Chen
发明人： Wenwu Wang , Shijie Chen , Xiaolei Wang , Kai Han , Dapeng Chen
IPC分类号： H01L21/3205 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/28176 , H01L29/4916 , H01L29/4966 , H01L29/4975 , H01L29/513 , H01L29/517
摘要： The present invention relates to a method of manufacturing a semiconductor device. After depositing the metal gate electrode material, a layer of oxygen molecule catalyzing layer having a catalyzing function to the oxygen molecules is deposited, and afterwards, a low-temperature PMA annealing process is used to decompose the oxygen molecules in the annealing atmosphere into more active oxygen atoms. These oxygen atoms are diffused into the high-k gate dielectric film through the metal gate to supplement the oxygen vacancies in the high-k film, in order to alleviate oxygen vacancies in the high-k film and improve the quality of the high-k film. According to the present invention, the oxygen vacancies and defects of high-k gate dielectric film will be alleviated, and further, growth of SiOx interface layer having a low dielectric constant caused by the traditional PDA high temperature process may be prevented. Thereby, the EOT of the entire gate dielectric layer may be effectively controlled, and the MOS device may be continuously scaled. Meanwhile, the present invention further provides a semiconductor device obtained according to the above-mentioned method.
摘要翻译：本发明涉及半导体器件的制造方法。沉积金属栅电极材料后，沉积具有对氧分子具有催化功能的氧分子催化层，然后使用低温PMA退火工艺将退火气氛中的氧分子分解为更有活性的氧原子。这些氧原子通过金属栅极扩散到高k栅极电介质膜中，以补充高k膜中的氧空位，以便减轻高k膜中的氧空位并提高高k的质量电影。根据本发明，可以减轻高k栅极电介质膜的氧空位和缺陷，并且可以防止由传统的PDA高温过程引起的具有低介电常数的SiO x界面层的生长。由此，可以有效地控制整个栅介质层的EOT，并且可以连续地缩放MOS器件。同时，本发明还提供了根据上述方法获得的半导体器件。

9. 发明授权

US08633098B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08633098B2
公开(公告)日：2014-01-21
申请号：US13061774
申请日：2010-09-28
申请人： Kai Han , Wenwu Wang , Xiaolei Wang , Shijie Chen , Dapeng Chen
发明人： Kai Han , Wenwu Wang , Xiaolei Wang , Shijie Chen , Dapeng Chen
IPC分类号： H01L21/28
CPC分类号： H01L29/4908 , H01L21/28176 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.
摘要翻译：本发明涉及半导体制造领域。本发明提供一种制造半导体器件的方法，其包括：提供半导体衬底; 在基板上形成界面层，栅极电介质层和栅电极; 在栅电极上形成金属氧吸收层; 对半导体器件进行热退火处理，使得金属氧吸收层吸收界面层中的氧，并且界面层的厚度减小。通过本发明，一方面可以减小界面层的厚度，另一方面，通过金属氧化物吸收层中的金属氧化物吸收层中的金属扩散到栅电极和/或栅电介质层退火工艺，进一步实现了调节有效功函数和控制阈值电压的效果。

10. 发明申请

US20120021596A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120021596A1
公开(公告)日：2012-01-26
申请号：US13061774
申请日：2010-09-28
申请人： Kai Han , Wenwu Wang , Xiaolei Wang , Shijie Chen , Dapeng Chen
发明人： Kai Han , Wenwu Wang , Xiaolei Wang , Shijie Chen , Dapeng Chen
IPC分类号： H01L21/28
CPC分类号： H01L29/4908 , H01L21/28176 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.
摘要翻译：本发明涉及半导体制造领域。本发明提供一种制造半导体器件的方法，其包括：提供半导体衬底; 在基板上形成界面层，栅极电介质层和栅电极; 在栅电极上形成金属氧吸收层; 对半导体器件进行热退火处理，使得金属氧吸收层吸收界面层中的氧，并且界面层的厚度减小。通过本发明，一方面可以减小界面层的厚度，另一方面，通过金属氧化物吸收层中的金属氧化物吸收层中的金属扩散到栅电极和/或栅电介质层退火工艺，进一步实现了调节有效功函数和控制阈值电压的效果。

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