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1. 发明申请

US20130109186A1 METHOD OF FORMING SEMICONDUCTOR DEVICES USING SMT 审中-公开
标题翻译：使用SMT形成半导体器件的方法
公开(公告)号：US20130109186A1
公开(公告)日：2013-05-02
申请号：US13662277
申请日：2012-10-26
申请人： Wenguang ZHANG , Qiang XU , Chunsheng Zheng , Lingzhi Xu , Yuwen Chen
发明人： Wenguang ZHANG , Qiang XU , Chunsheng Zheng , Lingzhi Xu , Yuwen Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/3105 , H01L21/823807 , H01L29/7843 , H01L29/7847
摘要： The present invention provides a method of forming semiconductor devices using SMT. The method comprises providing a substrate; depositing an SiO2 buffer film and a low tensile stress SiN film on the substrate; applying photoresist over the low tensile stress SiN film and exposing the low tensile stress SiN film on the NMOS region through photoresist exposure; applying UV radiation to the exposed low tensile stress SiN film; removing some hydrogen in the low tensile stress SiN film on the NMOS region and removing photoresist over the PMOS region; performing a rapid thermal annealing process to induce tensile stress in the NMOS channel region; and removing the SiN film and the SiO2 buffer film. According to the method of forming semiconductor devices using SMT of the present invention, the conventional SMT is greatly simplified.
摘要翻译：本发明提供使用SMT形成半导体器件的方法。该方法包括提供基底; 在衬底上沉积SiO 2缓冲膜和低拉伸应力SiN膜; 在低拉伸应力SiN膜上施加光致抗蚀剂，并通过光致抗蚀剂曝光使NMOS区域上的低拉伸应力SiN膜暴露; 对暴露的低拉伸应力SiN膜施加紫外线辐射; 去除NMOS区域上的低拉伸应力SiN膜中的一些氢，并去除PMOS区域上的光致抗蚀剂; 执行快速热退火工艺以在NMOS沟道区域中引起拉伸应力; 并且去除SiN膜和SiO 2缓冲膜。根据使用本发明的使用SMT的半导体器件的方法，传统的SMT被大大简化。

2. 发明申请

US20130078806A1 Method for Fabricating Copper Interconnections in an Ultra Low Dielectric Constant Film 审中-公开
标题翻译：在超低介电常数膜中制造铜互连的方法
公开(公告)号：US20130078806A1
公开(公告)日：2013-03-28
申请号：US13339736
申请日：2011-12-29
申请人： Yuwen Chen , Qiang Xu , Chunsheng Zheng , Wenguang Zhang
发明人： Yuwen Chen , Qiang Xu , Chunsheng Zheng , Wenguang Zhang
IPC分类号： H01L21/768
CPC分类号： H01L21/76801 , H01L21/76811 , H01L21/76813
摘要： The invention relates to a method for fabricating copper interconnections in an ultra low dielectric constant film, comprising the following steps of: depositing an etching stop layer on a silicon wafer, depositing an ultra-low-k film on the etching stop layer, and depositing a SiO2-riched layer on the ultra-low-k film; forming a via and/or trench that penetrates through the SiO2-riched layer and the ultra-low-k film by using a photo-lithography and etching process; sputter-depositing a metal barrier layer and a copper seed crystal layer within the via and/or trench, performing a copper filling deposition by an electroplating process, performing a chemical mechanical polishing until the SiO2-riched layer is reached, whereby forming a copper interconnection layer. Since the SiO2-riched layer and the ultra-low-k film can be deposited in the same tool, this method has the , advantages of shortening the production period, lowering the production cost and improving the adhesion in the copper interconnection structure.
摘要翻译：本发明涉及一种在超低介电常数膜中制造铜互连的方法，包括以下步骤：在硅晶片上沉积蚀刻停止层，在蚀刻停止层上沉积超低k膜，并沉积超低k膜上的SiO 2富集层; 通过使用光刻和蚀刻工艺形成穿透SiO 2层和超低k膜的通孔和/或沟槽; 在通孔和/或沟槽内溅射沉积金属阻挡层和铜籽晶层，通过电镀工艺执行铜填充沉积，进行化学机械抛光，直到达到SiO2-富集层，从而形成铜互连层。由于SiO2-层和超低k膜可以沉积在相同的工具中，所以该方法具有缩短生产周期，降低生产成本和提高铜互连结构中的附着力的优点。

3. 发明授权

US08426288B2 Method for improving capacitance uniformity in a MIM device 有权
标题翻译：用于改善MIM器件中的电容均匀性的方法
公开(公告)号：US08426288B2
公开(公告)日：2013-04-23
申请号：US13339406
申请日：2011-12-29
申请人： Qiang Xu , Wenguang Zhang , Chunsheng Zheng , Yuwen Chen
发明人： Qiang Xu , Wenguang Zhang , Chunsheng Zheng , Yuwen Chen
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , C23C16/345 , C23C16/45523 , C23C16/505 , C23C16/56
摘要： A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step S6 may be repeated for several times as needed. According to the method for improving capacitance uniformity in a MIM device of the present invention, a certain quantity of defects in the thin film are removed by means of several times of deposition/plasma processes based on the current PECVD, and uniformity of the deposited thin film is increased, thereby improving uniformity in wet etching rate of the thin film and further improving capacitance uniformity in the MIM device.
摘要翻译：主要用于提高MIM器件内的薄膜均匀性的MIM器件中的电容均匀性的改善方法包括8个步骤，并且步骤S2的步骤S6可根据需要重复多次。根据本发明的MIM器件中的电容均匀性的提高方法，通过基于当前PECVD的多次沉积/等离子体处理，去除薄膜中的一定量的缺陷，并且沉积的薄膜膜增加，从而提高了薄膜的湿蚀刻速度的均匀性，并且进一步提高了MIM器件中的电容均匀性。

4. 发明授权

US08927350B2 Integration flow for LDD and spacer fabrication on a sacrificial amorphous carbon gate structure 有权
标题翻译：在牺牲非晶碳栅极结构上的LDD和间隔物制造的集成流程
公开(公告)号：US08927350B2
公开(公告)日：2015-01-06
申请号：US13716990
申请日：2012-12-17
申请人： Chunsheng Zheng
发明人： Chunsheng Zheng
IPC分类号： H01L21/00 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823828 , H01L21/823864
摘要： An integration flow for LDD and spacer fabrication on a sacrificial amorphous carbon gate structure, form first spacer by way of depositing on the si substrate which have gate structure first. Gate is provided above the N-well and P-well on substrate. Spin coating a layer of photoresist in the first spacer, patterning the photoresist, and the gate structure above the N-well or P-well is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the first spacer layer, form the second spacer layer by depositing on the surface of the si substrate and gate, and spin coating another photoresist layer on the second spacer layer. Pattern the another photoresist layer, and another side of the gate structure is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the second spacer layer, form the third spacer layer and SiN layer by depositing on the gate and the Si substrate in turn. Form spacer by removing the redundant the third spacer layer and SiN layer.
摘要翻译：在牺牲非晶碳栅极结构上的LDD和间隔物制造的集成流程通过沉积在首先具有栅极结构的si衬底上的第一间隔物形成。栅极设置在衬底上的N阱和P阱的上方。在第一间隔物中旋涂一层光致抗蚀剂，对光致抗蚀剂进行图案化，并露出N阱或P阱上方的栅极结构，然后将离子轻质掺杂处理用于整个器件。去除冗余的光致抗蚀剂和第一间隔层，通过在si衬底和栅极的表面上沉积形成第二间隔层，并在第二间隔层上旋涂另一个光致抗蚀剂层。对另一个光致抗蚀剂层进行图案化，另一侧的栅极结构被暴露，然后将离子轻质掺杂处理用于整个器件。通过在栅极和Si衬底上依次沉积去除冗余光致抗蚀剂和第二间隔层，形成第三间隔层和SiN层。通过去除冗余的第三间隔层和SiN层来形成间隔物。

5. 发明申请

US20130273702A1 Integration Flow For LDD And Spacer Fabrication On A Sacrificial Amorphous Carbon Gate Structure 有权
标题翻译：一个牺牲无定形碳门结构的LDD和隔板制造的集成流程
公开(公告)号：US20130273702A1
公开(公告)日：2013-10-17
申请号：US13716990
申请日：2012-12-17
申请人： Chunsheng Zheng
发明人： Chunsheng Zheng
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823828 , H01L21/823864
摘要： An integration flow for LDD and spacer fabrication on a sacrificial amorphous carbon gate structure, form first spacer by way of depositing on the si substrate which have gate structure first. Gate is provided above the N-well and P-well on substrate. Spin coating a layer of photoresist in the first spacer, patterning the photoresist, and the gate structure above the N-well or P-well is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the first spacer layer, form the second spacer layer by depositing on the surface of the si substrate and gate, and spin coating another photoresist layer on the second spacer layer. Pattern the another photoresist layer, and another side of the gate structure is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the second spacer layer, form the third spacer layer and SiN layer by depositing on the gate and the Si substrate in turn. Form spacer by removing the redundant the third spacer layer and SiN layer.
摘要翻译：在牺牲非晶碳栅极结构上的LDD和间隔物制造的集成流程通过沉积在首先具有栅极结构的si衬底上的第一间隔物形成。栅极设置在衬底上的N阱和P阱的上方。在第一间隔物中旋涂一层光致抗蚀剂，对光致抗蚀剂进行图案化，并露出N阱或P阱上方的栅极结构，然后将离子轻质掺杂处理用于整个器件。去除冗余的光致抗蚀剂和第一间隔层，通过在si衬底和栅极的表面上沉积形成第二间隔层，并在第二间隔层上旋涂另一个光致抗蚀剂层。对另一个光致抗蚀剂层进行图案化，另一侧的栅极结构被暴露，然后将离子轻质掺杂处理用于整个器件。通过在栅极和Si衬底上依次沉积去除冗余光致抗蚀剂和第二间隔层，形成第三间隔层和SiN层。通过去除冗余的第三间隔层和SiN层来形成间隔物。

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