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1. 发明授权

US06350694B1 Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials 有权
标题翻译：对于低k材料，通过后CMP回蚀法减少CMP划痕，凹陷和侵蚀
公开(公告)号：US06350694B1
公开(公告)日：2002-02-26
申请号：US09814038
申请日：2001-03-22
申请人： Weng Chang , Tien-I Bao , Syun-Ming Jang
发明人： Weng Chang , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： G11C11/406 , G11C11/404 , G11C11/40603 , G11C11/4096 , H01L21/02074 , H01L21/31055 , H01L21/31058 , H01L21/3212 , H01L21/76819 , H01L21/7684
摘要： A new plasma etch back is provided that is applied to the surface of a low-k dielectric after the process of CMP of a copper surface has been completed. The copper surface is the surface of interconnect metal, the interconnect metal is embedded in the layer of low-k dielectric.
摘要翻译：提供了一种新的等离子体回蚀，其在铜表面的CMP处理已经完成之后被施加到低k电介质的表面。铜表面是互连金属的表面，互连金属嵌入在低k电介质层中。

2. 发明授权

US06518183B1 Hillock inhibiting method for forming a passivated copper containing conductor layer 有权
标题翻译：用于形成钝化含铜导体层的起丘抑制方法
公开(公告)号：US06518183B1
公开(公告)日：2003-02-11
申请号：US09947782
申请日：2001-09-06
申请人： Weng Chang , Tien-I Bao , Ying-Ho Chen , Syun-Ming Jang
发明人： Weng Chang , Tien-I Bao , Ying-Ho Chen , Syun-Ming Jang
IPC分类号： H01L2144
CPC分类号： H01L21/76883 , H01L21/76834
摘要： Within a method for fabricating a microelectronic fabrication having formed therein a copper containing conductor layer passivated with a passivation layer, there is first: (1) pre-heated the copper containing conductor layer to a temperature of from about 300 to about 450 degrees centigrade for a time period of from about 30 to about 120 seconds to form a pre-heated copper containing conductor layer; and then (2) plasma treated the pre-heated copper containing conductor layer within a reducing plasma to form a plasma treated pre-heated copper containing conductor layer; prior to (3)forming upon the plasma treated pre-heated copper containing conductor layer the passivation layer. The foregoing process sequence provides for attenuated hillock defects within the plasma treated pre-heated copper containing conductor layer when forming the passivation layer thereupon.
摘要翻译：在其中形成有钝化层钝化的含铜导体层的微电子制造方法中，首先：（1）将含铜导体层预热至约300至约450摄氏度的温度，用于约30至约120秒的时间段以形成预热的含铜导体层; 然后（2）在还原等离子体中等离子体处理预热的含铜导体层，以形成等离子体处理的预热含铜导体层; 在（3）在等离子体处理的预热含铜导体层上形成钝化层之前。当在其上形成钝化层时，上述工艺顺序提供等离子体处理的预热含铜导体层内的衰减的小丘缺陷。

3. 发明授权

US06472312B2 Methods for inhibiting microelectronic damascene processing induced low dielectric constant dielectric layer physical degradation 有权
标题翻译：抑制微电子镶嵌加工的方法诱导低介电常数介电层物理降解
公开(公告)号：US06472312B2
公开(公告)日：2002-10-29
申请号：US09761485
申请日：2001-01-16
申请人： Tien-I Bao , Syun-Ming Jang , Weng Chang
发明人： Tien-I Bao , Syun-Ming Jang , Weng Chang
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/76807 , H01L21/76829 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Within a series of chemical mechanical polish (CMP) planarizing methods for forming a series of damascene structures within a series of microelectronic fabrications, there is employed at least one lateral offset width between: (1) a sidewall of a patterned dielectric layer and an edge of a substrate; (2) a sidewall of a patterned conductor layer and a sidewall of a patterned dielectric layer; and (3) a sidewall of a patterned second dielectric layer and a sidewall of a first dielectric layer. By employing the at least one lateral offset, there is provided the series of damascene structures with inhibited physical degradation of a patterned dielectric layer when forming within an aperture defined by the patterned dielectric layer a chemical mechanical polish (CMP) planarized patterned conductor layer.
摘要翻译：在一系列用于在一系列微电子制造中形成一系列镶嵌结构的化学机械抛光（CMP）平面化方法中，采用至少一个横向偏移宽度：（1）图案化介电层的侧壁和边缘的基材; （2）图案化导体层的侧壁和图案化介电层的侧壁; 和（3）图案化的第二介电层的侧壁和第一介电层的侧壁。通过采用至少一个横向偏移，提供了一系列镶嵌结构，当在由图案化的介电层限定的孔内形成化学机械抛光（CMP）平面化图案化导体层时，图案化介电层的物理降解被抑制。

4. 发明授权

US07456093B2 Method for improving a semiconductor device delamination resistance 有权
标题翻译：提高半导体器件耐分层性的方法
公开(公告)号：US07456093B2
公开(公告)日：2008-11-25
申请号：US10884719
申请日：2004-07-03
申请人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
发明人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L23/53295 , H01L21/76801 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/3135 , H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.
摘要翻译：具有改进的分层耐受性的半导体器件及其形成方法包括提供包含具有最上蚀刻停止层的金属化层的半导体晶片的方法; 在所述蚀刻停止层上形成至少一个附着促进层; 以及在所述至少一个附着促进层上形成金属间电介质（IMD）层。

5. 发明申请

US20070264843A1 Formation and applications of nitrogen-free silicon carbide in semiconductor manufacturing 审中-公开
标题翻译：半导体制造中无氮碳化硅的形成与应用
公开(公告)号：US20070264843A1
公开(公告)日：2007-11-15
申请号：US11430623
申请日：2006-05-09
申请人： Lih-Ping Li , Yung-Cheng Lu , Tien-I. Bao , Syun-Ming Jang , Ying-Tsung Chen
发明人： Lih-Ping Li , Yung-Cheng Lu , Tien-I. Bao , Syun-Ming Jang , Ying-Tsung Chen
IPC分类号： H01L21/31
CPC分类号： H01L21/02126 , H01L21/02167 , H01L21/02216 , H01L21/02274 , H01L21/02362 , H01L21/31144 , H01L21/3148 , H01L21/31604 , H01L21/76829
摘要： A method for manufacturing an integrated circuit is provided. In one example, the method includes forming a substantially nitrogen-free silicon carbide layer over a substrate using a methyl silicate gas.
摘要翻译：提供一种用于制造集成电路的方法。在一个实例中，该方法包括使用甲基硅酸盐气体在基底上形成基本上无氮的碳化硅层。

6. 发明授权

US07015136B2 Method for preventing formation of photoresist scum 有权
标题翻译：防止光刻胶浮渣形成的方法
公开(公告)号：US07015136B2
公开(公告)日：2006-03-21
申请号：US10618219
申请日：2003-07-10
申请人： Tien-I Bao , Shwang-Min Jeng , Syun-Ming Jang
发明人： Tien-I Bao , Shwang-Min Jeng , Syun-Ming Jang
IPC分类号： H01L21/302
CPC分类号： G03F7/091 , Y10S438/95
摘要： A method for preventing formation of photoresist scum. First, a substrate on which a dielectric layer is formed is provided. Next, a non-nitrogen anti-reflective layer is formed on the dielectric layer. Finally, a photoresist pattern layer is formed on the non-nitrogen anti-reflective layer. During the formation of the photoresist pattern layer, the non-nitrogen anti-reflective layer does not react with the photoresist pattern layer, thus not forming photoresist scum. This prevents undesired etching profile and critical dimension (CD) change due to presence of photoresist scum. The non-nitrogen anti-reflective layer can be silicon-rich oxide (SiOx) or hydrocarbon-containing silicon-rich oxide (SiOxCy:H).
摘要翻译：防止光刻胶浮渣形成的方法。首先，提供形成介电层的基板。接下来，在电介质层上形成非氮抗反射层。最后，在非氮抗反射层上形成光刻胶图形层。在形成光致抗蚀剂图案层期间，非氮抗反射层不与光致抗蚀剂图案层反应，因此不形成光致抗蚀剂浮渣。这防止由于存在光致抗蚀剂浮渣而引起的不期望的蚀刻轮廓和临界尺寸（CD）变化。非氮抗反射层可以是富氧氧化物（SiO 2）或含烃的富含氧的氧化物（SiO x x C y） SUB>：H）。

7. 发明申请

US20060003572A1 Method for improving a semiconductor device delamination resistance 有权
标题翻译：提高半导体器件耐分层性的方法
公开(公告)号：US20060003572A1
公开(公告)日：2006-01-05
申请号：US10884719
申请日：2004-07-03
申请人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
发明人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76801 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/3135 , H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.
摘要翻译：具有改进的分层耐受性的半导体器件及其形成方法包括提供包含具有最上蚀刻停止层的金属化层的半导体晶片的方法; 在所述蚀刻停止层上形成至少一个附着促进层; 以及在所述至少一个附着促进层上形成金属间电介质（IMD）层。

8. 发明授权

US06962869B1 SiOCH low k surface protection layer formation by CxHy gas plasma treatment 有权
标题翻译： SiOCH低k表面保护层通过CxHy气体等离子体处理形成
公开(公告)号：US06962869B1
公开(公告)日：2005-11-08
申请号：US10270974
申请日：2002-10-15
申请人： Tien-I Bao , Hsin-Hsien Lu , Lih-Ping Li , Chung-Chi Ko , Aaron Song , Syun-Ming Jang
发明人： Tien-I Bao , Hsin-Hsien Lu , Lih-Ping Li , Chung-Chi Ko , Aaron Song , Syun-Ming Jang
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/3105 , H01L21/31144 , H01L21/3212 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76835
摘要： A method of protecting a low k dielectric layer that is preferably comprised of a material containing Si, O, C, and H is described. The dielectric layer is subjected to a gas plasma that is generated from a CXHY gas which is preferably ethylene. Optionally, hydrogen may be added to the CXHY gas. Another alternative is a two step plasma process involving a first plasma treatment of CXHY or CXHY combined with H2 and a second plasma treatment with H2. The modified dielectric layer provides improved adhesion to anti-reflective layers and to a barrier metal layer in a damascene process. The modified dielectric layer also has a low CMP rate that prevents scratch defects and an oxide recess from occurring next to the metal layer on the surface of the damascene stack. The plasma treatments are preferably done in the same chamber in which the dielectric layer is deposited.
摘要翻译：描述了保护低k电介质层的方法，其优选由含有Si，O，C和H的材料组成。对电介质层进行气化等离子体，该等离子体是由优选乙烯的C X H Y气产生的。任选地，可以将氢气加入到C 1 H 2 H 2 O气体中。另一种替代方案是涉及第一等离子体处理C X> Y Y or SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB >与H 2 H 2结合，并且与H 2 2进行第二等离子体处理。改进的介电层在镶嵌工艺中提供对抗反射层和阻挡金属层的改善的粘合性。改进的介电层也具有低CMP速率，其防止划痕缺陷和氧化物凹陷在镶嵌层的表面上邻近金属层发生。等离子体处理优选在沉积介电层的相同的室中进行。

9. 发明申请

US20050184288A1 Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method 审中-公开
标题翻译：半导体器件具有在第一级上形成的第二级金属化，对第一级具有最小的损伤和方法
公开(公告)号：US20050184288A1
公开(公告)日：2005-08-25
申请号：US10800510
申请日：2004-03-15
申请人： Tien-I Bao , Syun-Ming Jang
发明人： Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21/311 , H01L21/768 , H01L51/00
CPC分类号： H01L21/31116 , H01L21/76807 , H01L21/76829 , H01L21/76838
摘要： A semiconductor device having an upper level of metallization interconnected with a lower level of metallization and a method of forming the device is provided. Accordingly, the process of the invention includes capping the lower level of metallization with an thin stop layer having a thickness of less than 300 Å and preferably about 100 Å such that the etching and ashing processes of removing photoresist and intermediate portions of etch stop layer is accomplished without damage to the lower level metallization.
摘要翻译：提供了具有与较低金属化水平互连的金属化上位的半导体器件和形成器件的方法。因此，本发明的方法包括用厚度小于300埃，优选约为100的薄的阻挡层封盖较低级别的金属化，使得去除蚀刻和蚀刻停止层的中间部分的蚀刻和灰化过程是完成而不损坏较低级别的金属化。

10. 发明授权

US06812043B2 Method for forming a carbon doped oxide low-k insulating layer 有权
标题翻译：形成碳掺杂氧化物低k绝缘层的方法
公开(公告)号：US06812043B2
公开(公告)日：2004-11-02
申请号：US10131713
申请日：2002-04-25
申请人： Tien-I Bao , Chung-Chi Ko , Lih-Ping Li , Syun-Ming Jang
发明人： Tien-I Bao , Chung-Chi Ko , Lih-Ping Li , Syun-Ming Jang
IPC分类号： H01L2100
CPC分类号： H01L21/76826 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/02362 , H01L21/31633 , H01L21/76807
摘要： A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an oregano-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.
摘要翻译：一种用于半导体器件制造的具有降低的介电常数和增加的硬度的介电绝缘层的形成方法，包括提供具有在其上形成电介质绝缘层的工艺表面的半导体晶片; 根据CVD工艺沉积碳掺杂氧化物层的CVD工艺，其包括具有Si-O基团和Si-Ry基团的牛至硅烷前体，其中R是烷基或环烷基，y是与硅; 并且将碳掺杂的氧化物层暴露于氢等离子体处理一段时间，从而减少碳掺杂的氧化物层厚度，包括减少碳掺杂的氧化物层介电常数并增加碳掺杂的氧化物层的硬度。

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