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1. 发明授权

US08647925B2 Surface modification for handling wafer thinning process 有权
标题翻译：用于处理晶片薄化工艺的表面改性
公开(公告)号：US08647925B2
公开(公告)日：2014-02-11
申请号：US12792975
申请日：2010-06-03
申请人： Wen-Chih Chiou , Shau-Lin Shue , Weng-Jin Wu , Ju-Pin Hung
发明人： Wen-Chih Chiou , Shau-Lin Shue , Weng-Jin Wu , Ju-Pin Hung
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L21/6836 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L24/94 , H01L2221/6834 , H01L2224/0401 , H01L2224/05568 , H01L2224/13025 , H01L2224/131 , H01L2224/13144 , H01L2224/14181 , H01L2224/81001 , H01L2224/81005 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2224/94 , H01L2224/97 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2224/11 , H01L2224/81 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： A wafer is provided with a through via extending a portion of a substrate, an interconnect structure electrically connecting the through via, and a polyimide layer formed on the interconnect structure. Surface modification of the polyimide layer is the formation of a thin dielectric film on the polyimide layer by coating, plasma treatment, chemical treatment, or deposition methods. The thin dielectric film is adhered strongly to the polyimide layer, which can reduce the adhesion between the wafer surface and an adhesive layer formed in subsequent carrier attaching process.
摘要翻译：晶片设置有延伸基板的一部分的通孔，连接通孔的互连结构和形成在互连结构上的聚酰亚胺层。聚酰亚胺层的表面改性是通过涂覆，等离子体处理，化学处理或沉积方法在聚酰亚胺层上形成薄的电介质膜。薄的电介质膜牢固地粘附到聚酰亚胺层，这可以降低晶片表面和随后的载体附接过程中形成的粘合剂层之间的粘合性。

2. 发明授权

US08252665B2 Protection layer for adhesive material at wafer edge 有权
标题翻译：在晶片边缘的粘合剂材料保护层
公开(公告)号：US08252665B2
公开(公告)日：2012-08-28
申请号：US12769725
申请日：2010-04-29
申请人： Wen-Chih Chiou , Weng-Jin Wu , Shau-Lin Shue
发明人： Wen-Chih Chiou , Weng-Jin Wu , Shau-Lin Shue
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L23/49811 , H01L21/561 , H01L21/6836 , H01L21/76898 , H01L24/81 , H01L24/94 , H01L25/50 , H01L2221/6834 , H01L2221/68381 , H01L2224/81001 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/00
摘要： A wafer is attached to a carrier by using an adhesive layer, and a portion of the adhesive layer is exposed adjacent to an edge of the wafer. After thinning the wafer, a protection layer is provided to cover the exposed portion of the adhesive layer. A plurality of dies is bonded onto the thinned wafer, and then the thinned wafer and the dies are encapsulated with a molding compound.
摘要翻译：通过使用粘合剂层将晶片附接到载体，并且粘合剂层的一部分暴露于晶片的边缘附近。在使晶片变薄之后，提供保护层以覆盖粘合剂层的暴露部分。将多个模具结合到薄的晶片上，然后用模塑料封装薄化的晶片和模具。

3. 发明授权

US08441136B2 Protection layer for adhesive material at wafer edge 有权
标题翻译：在晶片边缘的粘合剂材料保护层
公开(公告)号：US08441136B2
公开(公告)日：2013-05-14
申请号：US13560200
申请日：2012-07-27
申请人： Wen-Chih Chiou , Weng-Jin Wu , Shau-Lin Shue
发明人： Wen-Chih Chiou , Weng-Jin Wu , Shau-Lin Shue
IPC分类号： H01L23/29
CPC分类号： H01L23/49811 , H01L21/561 , H01L21/6836 , H01L21/76898 , H01L24/81 , H01L24/94 , H01L25/50 , H01L2221/6834 , H01L2221/68381 , H01L2224/81001 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/00
摘要： This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies.
摘要翻译：本说明书涉及包括具有第一表面和与第一表面相对的第二表面的晶片的半导体器件和通过粘合剂层附着到晶片的第一表面的载体，粘合剂层的与边缘的边缘相邻的部分晶片暴露。半导体器件还包括保护层以覆盖粘合剂层的暴露部分。半导体器件还包括附接到第二表面的多个管芯和封装多个管芯的模制化合物。

4. 发明授权

US08791549B2 Wafer backside interconnect structure connected to TSVs 有权
标题翻译：晶圆背面互连结构连接到TSV
公开(公告)号：US08791549B2
公开(公告)日：2014-07-29
申请号：US12832019
申请日：2010-07-07
申请人： Ming-Fa Chen , Wen-Chih Chiou , Shau-Lin Shue
发明人： Ming-Fa Chen , Wen-Chih Chiou , Shau-Lin Shue
IPC分类号： H01L29/40 , H01L23/48 , H01L23/52
CPC分类号： H01L24/81 , H01L21/76807 , H01L21/76813 , H01L21/76816 , H01L21/76841 , H01L21/76843 , H01L21/76877 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05025 , H01L2224/05546 , H01L2224/05547 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/13144 , H01L2224/13155 , H01L2224/14181 , H01L2224/811 , H01L2224/8136 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
摘要翻译：集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。金属线包括双镶嵌结构。集成电路结构还包括覆盖金属线的凸块。

5. 发明申请

US20110068466A1 Wafer Backside Interconnect Structure Connected to TSVs 有权
标题翻译：晶圆背板互连结构连接到TSV
公开(公告)号：US20110068466A1
公开(公告)日：2011-03-24
申请号：US12832019
申请日：2010-07-07
申请人： Ming-Fa Chen , Wen-Chih Chiou , Shau-Lin Shue
发明人： Ming-Fa Chen , Wen-Chih Chiou , Shau-Lin Shue
IPC分类号： H01L23/498
CPC分类号： H01L24/81 , H01L21/76807 , H01L21/76813 , H01L21/76816 , H01L21/76841 , H01L21/76843 , H01L21/76877 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05025 , H01L2224/05546 , H01L2224/05547 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/13144 , H01L2224/13155 , H01L2224/14181 , H01L2224/811 , H01L2224/8136 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
摘要翻译：集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。金属线包括双镶嵌结构。集成电路结构还包括覆盖金属线的凸块。

6. 发明授权

US06736701B1 Eliminate broken line damage of copper after CMP 失效
标题翻译：消除CMP后的铜线损伤
公开(公告)号：US06736701B1
公开(公告)日：2004-05-18
申请号：US09989838
申请日：2001-11-20
申请人： Shau-Lin Shue , Ying-Ho Chen , Wen-Chih Chiou , Tsu Shih , Syun-Ming Jang
发明人： Shau-Lin Shue , Ying-Ho Chen , Wen-Chih Chiou , Tsu Shih , Syun-Ming Jang
IPC分类号： B24B100
CPC分类号： B24B37/042 , B24B21/04
摘要： A new method is provided for the post-deposition treatment of copper lines. A damascene copper line pattern whereby a TaN barrier layer and a seed layer have been provided is polished. Under the first embodiment of the invention, the deposited copper is polished (Cu CMP), the surface of the wafer is rinsed using a first High Flow DI rinse that contains a TBA inhibitor. The TaN CMP is performed immediately following the first High Flow DI rinse. A second High Flow DI rinse is applied using DI water that contains TBA inhibitor. The required following rinse step is executed immediately after the second High Flow DI rinse has been completed. Under the second embodiment of the invention, the process of CMP has been divided in two distinct steps where the first step is aimed at corrosion elimination and the second step is aimed at elimination of mechanical damage to the polished copper. The processing conditions for the second processing step have been extended and optimized, thereby using a second belt of a CMP apparatus.
摘要翻译：提供了一种新的铜线后处理方法。抛光已经提供TaN阻挡层和种子层的镶嵌铜线图案。在本发明的第一实施例中，抛光沉积的铜（Cu CMP），使用含有TBA抑制剂的第一高流量DI冲洗冲洗晶片的表面。在第一次高流量DI冲洗之后立即执行TaN CMP。使用含有TBA抑制剂的去离子水进行第二次高流量DI冲洗。第二次高流量DI冲洗完成后立即执行所需的冲洗步骤。在本发明的第二个实施方案中，CMP的方法分为两个不同的步骤，其中第一步骤旨在消除腐蚀，第二步骤旨在消除抛光铜的机械损伤。第二处理步骤的处理条件已被扩展和优化，从而使用CMP设备的第二带。

7. 发明授权

US07883991B1 Temporary carrier bonding and detaching processes 有权
标题翻译：临时运营商的绑定和拆卸流程
公开(公告)号：US07883991B1
公开(公告)日：2011-02-08
申请号：US12707752
申请日：2010-02-18
申请人： Wen-Jin Wu , Wen-Chih Chiou , Shau-Lin Shue
发明人： Wen-Jin Wu , Wen-Chih Chiou , Shau-Lin Shue
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/01019 , H01L2924/01077 , H01L2924/01078 , H01L2924/09701 , H01L2924/1461 , H01L2924/19041 , H01L2924/00 , H01L2224/05552
摘要： A method of bonding and detaching a temporary carrier used for handling a wafer during the fabrication of semiconductor devices includes bonding a wafer onto a carrier through a first adhesive layer and a second adhesive layer, in which the edge zone of the wafer and the carrier is covered by the first adhesive layer while the edge zone is not covered by the second adhesive layer. A wafer edge clean process is then performed to remove the first adhesive layer adjacent the edge of the wafer and expose the edge zone of the carrier, followed by removing the second adhesive layer from the carrier. After detaching the carrier from the wafer, the first adhesive layer remaining on the wafer is removed.
摘要翻译：在半导体器件的制造期间，接合和分离用于处理晶片的临时载体的方法包括通过第一粘合剂层和第二粘合剂层将晶片接合到载体上，其中晶片和载体的边缘区域被第一粘合剂层覆盖，而边缘区域不被第二粘合剂层覆盖。然后进行晶片边缘清洁工艺以除去邻近晶片边缘的第一粘合剂层，并暴露载体的边缘区域，然后从载体上除去第二粘合剂层。在从晶片上分离载体之后，去除残留在晶片上的第一粘合剂层。

8. 发明授权

US08252682B2 Method for thinning a wafer 有权
标题翻译：减薄晶片的方法
公开(公告)号：US08252682B2
公开(公告)日：2012-08-28
申请号：US12704695
申请日：2010-02-12
申请人： Ku-Feng Yang , Weng-Jin Wu , Hsin-Hsien Lu , Chia-Lin Yu , Chu-Sung Shih , Fu-Chi Hsu , Shau-Lin Shue
发明人： Ku-Feng Yang , Weng-Jin Wu , Hsin-Hsien Lu , Chia-Lin Yu , Chu-Sung Shih , Fu-Chi Hsu , Shau-Lin Shue
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76898 , H01L2224/02372
摘要： A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.
摘要翻译：提供了一种用于薄化晶片的方法。在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。提供晶片载体以附接到晶片的第二侧。晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。此后，绝缘层沉积在隔离层上。然后将绝缘层平坦化以暴露TSV的顶部。电介质层沉积在晶片的平坦化第一侧上。在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。

9. 发明授权

US08791011B2 Through-silicon via structure formation process 有权
标题翻译：通硅结构形成工艺
公开(公告)号：US08791011B2
公开(公告)日：2014-07-29
申请号：US13775983
申请日：2013-02-25
申请人： Yung-Chi Lin , Weng-Jin Wu , Shau-Lin Shue
发明人： Yung-Chi Lin , Weng-Jin Wu , Shau-Lin Shue
IPC分类号： H01L21/4763
CPC分类号： H01L21/76871 , H01L21/76844 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2924/3011 , H01L2924/014 , H01L2924/00014
摘要： In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening.
摘要翻译：在此过程中，形成从半导体衬底的前表面延伸穿过半导体衬底的一部分的开口。金属种子层形成在开口的侧壁上。仅在金属种子层的一部分上形成阻挡层。在阻挡层和金属种子层上形成金属层以填充开口。

10. 发明授权

US08405201B2 Through-silicon via structure 有权
标题翻译：通硅结构
公开(公告)号：US08405201B2
公开(公告)日：2013-03-26
申请号：US12836720
申请日：2010-07-15
申请人： Yung-Chi Lin , Weng-Jin Wu , Shau-Lin Shue
发明人： Yung-Chi Lin , Weng-Jin Wu , Shau-Lin Shue
IPC分类号： H01L23/48
CPC分类号： H01L21/76871 , H01L21/76844 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2924/3011 , H01L2924/014 , H01L2924/00014
摘要： A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a block layer formed in a portion sandwiched between the metal layer and the metal seed layer. The block layer includes magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), cadmium (Cd), or combinations thereof.
摘要翻译：半导体衬底具有前表面和后表面，并且形成TSV结构以延伸穿过半导体衬底。 TSV结构包括金属层，围绕金属层的金属籽晶层，围绕金属种子层的阻挡层，以及形成在夹在金属层和金属籽晶层之间的部分中的阻挡层。阻挡层包括镁（Mg），铁（Fe），钴（Co），镍（Ni），钛（Ti），铬（Cr），钽（Ta），钨（W），镉（Cd）其组合。

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