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1. 发明授权

US08208332B2 Temperature compensation circuit and method for sensing memory 有权
标题翻译：温度补偿电路和感应存储器的方法
公开(公告)号：US08208332B2
公开(公告)日：2012-06-26
申请号：US12870313
申请日：2010-08-27
申请人： Wen-Chiao Ho , Ji-Yu Hung , Chun-Hsiung Hung , Shuo-Nan Hung
发明人： Wen-Chiao Ho , Ji-Yu Hung , Chun-Hsiung Hung , Shuo-Nan Hung
IPC分类号： G11C7/04
CPC分类号： G11C7/08 , G11C7/04
摘要： A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.
摘要翻译：补偿电路包括比较器和仿真电路。比较器具有第一端子和用于接收参考电压的第二端子。仿真电路耦合到比较器的第一端。仿真电路响应于温度，使得比较器在第一时间点输出读定时控制信号，或者在第二时间点输出读定时控制信号，第一时间点晚于第二时间点。

2. 发明申请

US20100322018A1 Temperature Compensation Circuit and Method for Sensing Memory 有权
标题翻译：温度补偿电路和感应存储器的方法
公开(公告)号：US20100322018A1
公开(公告)日：2010-12-23
申请号：US12870313
申请日：2010-08-27
申请人： Wen-Chiao Ho , Ji-Yu Hung , Chun-Hsiung Hung , Shuo-Nan Hung
发明人： Wen-Chiao Ho , Ji-Yu Hung , Chun-Hsiung Hung , Shuo-Nan Hung
IPC分类号： G11C7/04
CPC分类号： G11C7/08 , G11C7/04
摘要： A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.
摘要翻译：补偿电路包括比较器和仿真电路。比较器具有第一端子和用于接收参考电压的第二端子。仿真电路耦合到比较器的第一端。仿真电路响应于温度，使得比较器在第一时间点输出读定时控制信号，或者在第二时间点输出读定时控制信号，第一时间点晚于第二时间点。

3. 发明申请

US20100124136A1 TEMPERATURE COMPENSATION CIRCUIT AND METHOD FOR SENSING MEMORY 有权
标题翻译：温度补偿电路和感应记忆的方法
公开(公告)号：US20100124136A1
公开(公告)日：2010-05-20
申请号：US12271022
申请日：2008-11-14
申请人： Wen-Chiao Ho , Ji-Yu Hung , Chun-Hsiung Hung , Shuo-Nan Hung
发明人： Wen-Chiao Ho , Ji-Yu Hung , Chun-Hsiung Hung , Shuo-Nan Hung
IPC分类号： G11C7/04 , H03K3/02
CPC分类号： G11C7/08 , G11C7/04
摘要： A temperature compensation circuit includes a voltage generator, a comparator and an emulation cell array. The voltage generator provides a predetermined voltage and a reference voltage. The comparator has a first terminal for receiving the predetermined voltage, and a second terminal for receiving the reference voltage. The emulation cell array is coupled to the first terminal of the comparator. When a voltage of the first terminal of the comparator is discharged, via the emulation cell array, to be lower than the reference voltage, the comparator outputs a read timing control signal to control a sense amplifier to perform a sensing operation.
摘要翻译：温度补偿电路包括电压发生器，比较器和仿真单元阵列。电压发生器提供预定电压和参考电压。比较器具有用于接收预定电压的第一端子和用于接收参考电压的第二端子。仿真单元阵列耦合到比较器的第一端。当比较器的第一端子的电压经由仿真单元阵列放电到低于参考电压时，比较器输出读取定时控制信号以控制读出放大器执行感测操作。

4. 发明授权

US07804729B2 Temperature compensation circuit and method for sensing memory 有权
标题翻译：温度补偿电路和感应存储器的方法
公开(公告)号：US07804729B2
公开(公告)日：2010-09-28
申请号：US12271022
申请日：2008-11-14
申请人： Wen-Chiao Ho , Ji-Yu Hung , Chun-Hsiung Hung , Shuo-Nan Hung
发明人： Wen-Chiao Ho , Ji-Yu Hung , Chun-Hsiung Hung , Shuo-Nan Hung
IPC分类号： G11C7/04
CPC分类号： G11C7/08 , G11C7/04
摘要： A temperature compensation circuit includes a voltage generator, a comparator and an emulation cell array. The voltage generator provides a predetermined voltage and a reference voltage. The comparator has a first terminal for receiving the predetermined voltage, and a second terminal for receiving the reference voltage. The emulation cell array is coupled to the first terminal of the comparator. When a voltage of the first terminal of the comparator is discharged, via the emulation cell array, to be lower than the reference voltage, the comparator outputs a read timing control signal to control a sense amplifier to perform a sensing operation.
摘要翻译：温度补偿电路包括电压发生器，比较器和仿真单元阵列。电压发生器提供预定电压和参考电压。比较器具有用于接收预定电压的第一端子和用于接收参考电压的第二端子。仿真单元阵列耦合到比较器的第一端。当比较器的第一端子的电压经由仿真单元阵列放电到低于参考电压时，比较器输出读取定时控制信号以控制读出放大器执行感测操作。

5. 发明授权

US08924819B2 Memory device and operation method thereof 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US08924819B2
公开(公告)日：2014-12-30
申请号：US12358900
申请日：2009-01-23
申请人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G11C29/00 , G06F11/10 , G11C29/04
CPC分类号： G06F11/1072 , G11C29/00 , G11C2029/0411
摘要： A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device.
摘要翻译：提供了一种操作存储器件的方法，包括以下步骤。根据用户数据生成第一个纠错码。然后，将用户数据写入存储器件。此外，读取存储器件中的用户数据，并根据读取的用户数据生成第二纠错码。此外，将第一和第二纠错码写入存储器件。

6. 发明申请

US20110128786A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20110128786A1
公开(公告)日：2011-06-02
申请号：US12628710
申请日：2009-12-01
申请人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G11C16/14 , G11C16/04 , G11C16/06
CPC分类号： G11C16/16
摘要： A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines, wherein a first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.
摘要翻译：存储器件包括存储器扇区，其包括存储器扇区，一行选择晶体管和多个驱动器。存储器扇区包括多个字线，每个字线耦合到多个存储器单元。选择晶体管行选择存储器扇区，并将存储器扇区与存储器件中紧邻的存储器扇区分开。多个驱动器中的每一个耦合到多个字线中的一个，其中驱动器中的第一个耦合到字线中的第一个，以接收第一控制信号以传导第一字线和电压源并且驱动器中的第二个耦合到第二个字线以接收第二控制信号以将第二字线与电压源断开。

7. 发明申请

US20100192039A1 MEMORY DEVICE AND OPERATION METHOD THEREOF 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US20100192039A1
公开(公告)日：2010-07-29
申请号：US12358900
申请日：2009-01-23
申请人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/1072 , G11C29/00 , G11C2029/0411
摘要： A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device.
摘要翻译：提供了一种操作存储器件的方法，包括以下步骤。根据用户数据生成第一个纠错码。然后，将用户数据写入存储器件。此外，读取存储器件中的用户数据，并根据读取的用户数据生成第二纠错码。此外，将第一和第二纠错码写入存储器件。

8. 发明授权

US08270223B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08270223B2
公开(公告)日：2012-09-18
申请号：US12628710
申请日：2009-12-01
申请人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines. A first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.
摘要翻译：存储器件包括存储器扇区，其包括存储器扇区，一行选择晶体管和多个驱动器。存储器扇区包括多个字线，每个字线耦合到多个存储器单元。选择晶体管行选择存储器扇区，并将存储器扇区与存储器件中紧邻的存储器扇区分开。多个驱动器中的每一个耦合到多个字线中的一个。驱动器中的第一个被耦合到字线中的第一个以接收第一控制信号以传导第一字线和电压源，并且第二驱动器耦合到第二个字线以接收第二控制信号以将第二字线与电压源断开。

9. 发明申请

US20120182804A1 ARCHITECTURE FOR A 3D MEMORY ARRAY 有权
标题翻译： 3D存储阵列的架构
公开(公告)号：US20120182804A1
公开(公告)日：2012-07-19
申请号：US13245587
申请日：2011-09-26
申请人： CHUN-HSIUNG HUNG , Shuo-Nan Hung , Ji-Yu Hung , Shih-Lin Huang , Fu-Tsang Wang
发明人： CHUN-HSIUNG HUNG , Shuo-Nan Hung , Ji-Yu Hung , Shih-Lin Huang , Fu-Tsang Wang
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/26 , G11C2216/14 , H01L27/1157 , H01L27/11578
摘要： Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.
摘要翻译：这里描述了用于通过对选定的位线应用不同的偏置条件来补偿阵列中的存储器单元之间的阈值电压变化的技术。本文还描述了将全局位线连接到3D阵列中的各种级别的存储器单元的技术，以提供最小化全局位线之间的电容差。

10. 发明授权

US08724390B2 Architecture for a 3D memory array 有权
标题翻译： 3D内存阵列的架构
公开(公告)号：US08724390B2
公开(公告)日：2014-05-13
申请号：US13245587
申请日：2011-09-26
申请人： Chun-Hsiung Hung , Shuo-Nan Hung , Ji-Yu Hung , Shih-Lin Huang , Fu-Tsang Wang
发明人： Chun-Hsiung Hung , Shuo-Nan Hung , Ji-Yu Hung , Shih-Lin Huang , Fu-Tsang Wang
IPC分类号： G11C11/34
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/26 , G11C2216/14 , H01L27/1157 , H01L27/11578
摘要： Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.
摘要翻译：这里描述了用于通过对选定的位线应用不同的偏置条件来补偿阵列中的存储器单元之间的阈值电压变化的技术。本文还描述了将全局位线连接到3D阵列中的各种级别的存储器单元的技术，以提供最小化全局位线之间的电容差。

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