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1. 发明授权

US07580302B2 Parallel threshold voltage margin search for MLC memory application 有权
标题翻译：并行阈值电压裕度搜索MLC存储器应用
公开(公告)号：US07580302B2
公开(公告)日：2009-08-25
申请号：US11551974
申请日：2006-10-23
申请人： Wen Chiao Ho , Chin Hung Chang , Cheng-Chi Liu , Kuen-Long Chang , Chun Hsiung Hung
发明人： Wen Chiao Ho , Chin Hung Chang , Cheng-Chi Liu , Kuen-Long Chang , Chun Hsiung Hung
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/5642 , G11C16/04 , G11C29/50004 , G11C2211/5634 , G11C2211/5644
摘要： A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.
摘要翻译：用于确定存储器阵列中的读取电压余量的方法将从存储器阵列读取的数据产生的读取和编码与从加载数据生成的预期总和进行比较。读取电压（Vt）是步进的，将读取的和码与预期的和码进行比较，以确定提供匹配和码的Vt范围。当Vt跨过其范围时，以并行方式确定多个读取电压余量（即，MLC存储器阵列的多个编程电平之间的读取电压余量）。

2. 发明授权

US07468912B2 Multi-level-cell programming methods of non-volatile memories 有权
标题翻译：非易失性存储器的多级单元编程方法
公开(公告)号：US07468912B2
公开(公告)日：2008-12-23
申请号：US11624612
申请日：2007-01-18
申请人： Wen Chiao Ho , Chin Hung Chang , Kuen Long Chang , Chun Hsiung Hung
发明人： Wen Chiao Ho , Chin Hung Chang , Kuen Long Chang , Chun Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5671 , G11C16/0475 , G11C16/3459
摘要： The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level1).
摘要翻译：本发明提供了一种在氮化物俘获存储器单元的多位单元中改变多电平单元编程的顺序的新颖方法，其减少或消除了程序步骤之间的电压阈值偏移，同时避免了在读取窗口由互补位干扰引起。在第一实施例中，本发明按照以下顺序在具有四位的多位单元中编程多电平单元：编程第三程序级（level3），编程第一程序级（level1）和第二程序级别（level2）到级别1，并从第一程序级别编程第二程序级别。在第二实施例中，本发明按照以下顺序对具有四位的多比特单元中的多电平单元进行编程：编程第三程序级（level3），编程第二程序级（level2），并编程第一程序级（level1）。

3. 发明授权

US07426139B2 Dynamic program and read adjustment for multi-level cell memory array 有权
标题翻译：多级单元存储器阵列的动态程序和读取调整
公开(公告)号：US07426139B2
公开(公告)日：2008-09-16
申请号：US11555849
申请日：2006-11-02
申请人： Wen Chiao Ho , Chin Hung Chang , Kuen-Long Chang , Chun Hsiung Hung
发明人： Wen Chiao Ho , Chin Hung Chang , Kuen-Long Chang , Chun Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C2211/5621
摘要： A method for operating a multi-level cell (“MLC”) memory array of an integrated circuit (“IC”) programs first data into a first plurality of MLCs in the MLC memory array at a first programming level. Threshold voltages for the first plurality of MLCs are sensed, and an adjust code is set according to the threshold voltages. Second data is programmed into a second plurality of MLCs in the MLC memory array at a second programming level, the second plurality of MLCs having a program-verify value set according to the adjust code. In a further embodiment, a reference voltage for reading the second plurality of MLCs is set according to the adjust code.
摘要翻译：用于操作集成电路（“IC”）的多级单元（“MLC”）存储器阵列的方法在第一编程级将第一数据编程到MLC存储器阵列中的第一多个MLC中。感测第一多个MLC的阈值电压，并且根据阈值电压设置调整代码。第二数据在第二编程级别被编程到MLC存储器阵列中的第二多个MLC中，第二多个MLC具有根据调整代码设置的程序验证值。在另一实施例中，根据调整代码来设置用于读取第二多个MLC的参考电压。

4. 发明授权

US07180780B1 Multi-level-cell programming methods of non-volatile memories 有权
标题翻译：非易失性存储器的多级单元编程方法
公开(公告)号：US07180780B1
公开(公告)日：2007-02-20
申请号：US11281181
申请日：2005-11-17
申请人： Wen Chiao Ho , Chin Hung Chang , Kuen Long Chang , Chun Hsiung Hung
发明人： Wen Chiao Ho , Chin Hung Chang , Kuen Long Chang , Chun Hsiung Hung
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/12 , G11C11/5671 , G11C16/0475 , G11C16/3459
摘要： The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level 1).
摘要翻译：本发明提供了一种在氮化物俘获存储器单元的多位单元中改变多电平单元编程的顺序的新颖方法，其减少或消除了程序步骤之间的电压阈值偏移，同时避免了在读取窗口由互补位干扰引起。在第一实施例中，本发明按照以下顺序在具有四位的多位单元中编程多电平单元：编程第三程序级（level3），编程第一程序级（level1）和第二程序级别（level2）到级别1，并从第一程序级别编程第二程序级别。在第二实施例中，本发明按照以下顺序对具有四位的多比特单元中的多电平单元进行编程：编程第三程序级（level3），编程第二程序级（level2），并编程第一程序级（1级）。

5. 发明授权

US07130222B1 Nonvolatile memory with program while program verify 有权
标题翻译：非易失性存储器，程序验证程序
公开(公告)号：US07130222B1
公开(公告)日：2006-10-31
申请号：US11235881
申请日：2005-09-26
申请人： Wen Chiao Ho , Yi Chun Shih , Chin Hung Chang , Chun Hsiung Hung
发明人： Wen Chiao Ho , Yi Chun Shih , Chin Hung Chang , Chun Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： A page mode program sequence is described that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of a page of memory cells, while a program verify bias is applied to, and data is sensed from, a second part of the page. In this manner, a first part of the page is programmed, while a second part of the page is verified. This operation is followed by a second bias applying cycle, in which a program bias is applied to the second part of the page, while a program verify bias is applied to, and data is sensed from, the first part of the page.
摘要翻译：描述了包括第一和第二偏置施加周期的页面模式程序序列。在第一周期中，程序偏差被施加到一页存储器单元的第一部分，同时程序验证偏差被施加到页面的第二部分并且从该页面的第二部分感测数据。以这种方式，页面的第一部分被编程，而页面的第二部分被验证。该操作之后是第二偏置施加周期，其中将程序偏置施加到页面的第二部分，同时将程序验证偏差施加到页面的第一部分并且从页面的第一部分感测数据。

6. 发明授权

US07382656B2 Nonvolatile memory with program while program verify 有权
标题翻译：非易失性存储器，程序验证程序
公开(公告)号：US07382656B2
公开(公告)日：2008-06-03
申请号：US11552293
申请日：2006-10-24
申请人： Wen Chiao Ho , Yi Chun Shih , Chin Hung Chang , Chun Hsiung Hung
发明人： Wen Chiao Ho , Yi Chun Shih , Chin Hung Chang , Chun Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： A page mode program sequence is described that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of a page of memory cells, while a program verify bias is applied to, and data is sensed from, a second part of the page. In this manner, a first part of the page is programmed, while a second part of the page is verified. This operation is followed by a second bias applying cycle, in which a program bias is applied to the second part of the page, while a program verify bias is applied to, and data is sensed from, the first part of the page.
摘要翻译：描述了包括第一和第二偏置施加周期的页面模式程序序列。在第一周期中，程序偏差被施加到一页存储器单元的第一部分，同时程序验证偏差被施加到页面的第二部分并且从该页面的第二部分感测数据。以这种方式，页面的第一部分被编程，而页面的第二部分被验证。该操作之后是第二偏置施加周期，其中将程序偏置施加到页面的第二部分，同时将程序验证偏差施加到页面的第一部分并且从页面的第一部分感测数据。

7. 发明申请

US20070121386A1 Multi-Level-Cell Programming Methods of Non-Volatile Memories 有权
标题翻译：非易失性存储器的多级单元编程方法
公开(公告)号：US20070121386A1
公开(公告)日：2007-05-31
申请号：US11624612
申请日：2007-01-18
申请人： Wen Chiao Ho , Chin Chang , Kuen Chang , Chun Hung
发明人： Wen Chiao Ho , Chin Chang , Kuen Chang , Chun Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5671 , G11C16/0475 , G11C16/3459
摘要： The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level1).
摘要翻译：本发明提供了一种在氮化物俘获存储器单元的多位单元中改变多电平单元编程的顺序的新颖方法，其减少或消除了程序步骤之间的电压阈值偏移，同时避免了在读取窗口由互补位干扰引起。在第一实施例中，本发明以具有四位的多位单元按以下顺序对多电平单元进行编程：编程第三程序电平（电平3），编程第一程序电平（电平1）和第二程序级（级别2）到级别1，并且从第一程序级编程第二程序级。在第二实施例中，本发明按照以下顺序对具有四位的多位单元中的多电平单元进行编程：编程第三程序电平（级别3），编程第二程序电平（级别2），以及编程第一个程序级（1级）。

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