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1. 发明申请

US20050207106A1 Commutate silencer of computer system 有权
标题翻译：计算机系统的换向消声器
公开(公告)号：US20050207106A1
公开(公告)日：2005-09-22
申请号：US10926012
申请日：2004-08-26
申请人： Wei-Ming Chen , Chao-Jung Chen , Wen-Liang Huang , Kai-Hung Lin
发明人： Wei-Ming Chen , Chao-Jung Chen , Wen-Liang Huang , Kai-Hung Lin
IPC分类号： G06F1/16 , G06F1/20 , H05K7/20
CPC分类号： G06F1/20
摘要： A commutate silencer of a computer system is described. The commutate silencer of the computer system is installed at the back end of the computer system, and comprises a shield device, a commutate device and at least one partition. The shield device comprises a first shield and a second shield, in which the first shield comprises an opening, the first shield and the second shield construct a first cavity, and the first cavity includes a plurality of outlets. The commutate device comprises a frame and a plurality of commutate diversion plates, in which the frame construct a second cavity, the diversion plates traverse the second cavity, the second cavity has an inlet and a ventilated opening, and the ventilated opening is connected to the opening of the first shield. The at least one partition is located in the first cavity and the second cavity, so as to separate the inlet, the ventilated opening and the outlets into a plurality of sub-inlets, a plurality of sub-ventilated openings and a plurality of sub-outlets, respectively.
摘要翻译：描述了计算机系统的换向消音器。计算机系统的换向消音器安装在计算机系统的后端，并且包括屏蔽装置，整流装置和至少一个隔板。所述屏蔽装置包括第一屏蔽和第二屏蔽，其中所述第一屏蔽包括开口，所述第一屏蔽和所述第二屏蔽构成第一腔，并且所述第一腔包括多个出口。整流装置包括框架和多个换向转向板，框架构成第二空腔，分流板横穿第二空腔，第二空腔具有入口和通风开口，通风开口连接到打开第一个盾牌。所述至少一个隔板位于所述第一空腔和所述第二空腔中，以将所述入口，所述通风口和所述出口分离为多个子入口，多个次通风开口和多个子通道，分店。

2. 发明授权

US07161801B2 Commutate silencer of computer system 有权
标题翻译：计算机系统的换向消声器
公开(公告)号：US07161801B2
公开(公告)日：2007-01-09
申请号：US10926012
申请日：2004-08-26
申请人： Wei-Ming Chen , Chao-Jung Chen , Wen-Liang Huang , Kai-Hung Lin
发明人： Wei-Ming Chen , Chao-Jung Chen , Wen-Liang Huang , Kai-Hung Lin
IPC分类号： H05K7/20 , G10K11/16
CPC分类号： G06F1/20
摘要： A commutate silencer of a computer system is described. The commutate silencer of the computer system is installed at the back end of the computer system, and comprises a shield device, a commutate device and at least one partition. The shield device comprises a first shield and a second shield, in which the first shield comprises an opening, the first shield and the second shield construct a first cavity, and the first cavity includes a plurality of outlets. The commutate device comprises a frame and a plurality of commutate diversion plates, in which the frame construct a second cavity, the diversion plates traverse the second cavity, the second cavity has an inlet and a ventilated opening, and the ventilated opening is connected to the opening of the first shield. The at least one partition is located in the first cavity and the second cavity, so as to separate the inlet, the ventilated opening and the outlets into a plurality of sub-inlets, a plurality of sub-ventilated openings and a plurality of sub-outlets, respectively.
摘要翻译：描述了计算机系统的换向消音器。计算机系统的换向消音器安装在计算机系统的后端，并且包括屏蔽装置，整流装置和至少一个隔板。所述屏蔽装置包括第一屏蔽和第二屏蔽，其中所述第一屏蔽包括开口，所述第一屏蔽和所述第二屏蔽构成第一腔，并且所述第一腔包括多个出口。整流装置包括框架和多个换向转向板，框架构成第二空腔，分流板横穿第二空腔，第二空腔具有入口和通风开口，通风开口连接到打开第一个盾牌。所述至少一个隔板位于所述第一空腔和所述第二空腔中，以将所述入口，所述通风口和所述出口分离为多个子入口，多个次通风开口和多个子通道，分店。

3. 发明授权

US08564133B2 Chip package and method for forming the same 有权
标题翻译：芯片封装及其形成方法
公开(公告)号：US08564133B2
公开(公告)日：2013-10-22
申请号：US12860823
申请日：2010-08-20
申请人： Ying-Nan Wen , Baw-Ching Perng , Wei-Ming Chen , Shu-Ming Chang
发明人： Ying-Nan Wen , Baw-Ching Perng , Wei-Ming Chen , Shu-Ming Chang
IPC分类号： H01L23/52
CPC分类号： H01L23/3135 , H01L21/76898 , H01L23/147 , H01L23/3121 , H01L23/481 , H01L23/49827 , H01L24/16 , H01L24/24 , H01L24/28 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2224/24051 , H01L2224/24226 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/8314 , H01L2224/8385 , H01L2224/92 , H01L2224/92244 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/12041 , H01L2924/12044 , H01L2924/1461 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer.
摘要翻译：根据本发明的实施例，提供了一种芯片封装。芯片封装包括具有上表面和相对的下表面的半导体衬底，穿过半导体衬底的上表面和下表面的通孔，设置在半导体衬底的上表面上的芯片，覆盖所述通孔的侧壁电连接所述芯片，覆盖所述半导体衬底的上表面的第一绝缘层，覆盖所述半导体衬底的下表面的第二绝缘层和设置在所述半导体衬底的下表面上的接合结构半导体衬底，其中所述第二绝缘层的材料与所述第一绝缘层的材料不同。

4. 发明申请

US20120037226A1 SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：半导体基板
公开(公告)号：US20120037226A1
公开(公告)日：2012-02-16
申请号：US13278165
申请日：2011-10-20
申请人： MENG-HSIU WU , Yu-Wei Tai , Wei-Ming Chen
发明人： MENG-HSIU WU , Yu-Wei Tai , Wei-Ming Chen
IPC分类号： H01L31/0216
CPC分类号： H01L31/02168 , H01L31/028 , H01L31/03682 , H01L31/03685 , H01L31/03762 , H01L31/055 , H01L31/0682 , H01L31/072 , Y02E10/52 , Y02E10/545 , Y02E10/546 , Y02E10/547 , Y02E10/548
摘要： A semiconductor substrate includes a substrate, at least a semiconductor layer, a first anti-reflection layer, and a second anti-reflection layer. The semiconductor layer is disposed on the substrate. The first anti-reflection layer is disposed on the semiconductor layer. The second anti-reflection layer is disposed on the first anti-reflection layer. The second anti-reflection layer is a discontinuous layer with the capability of photon conversion.
摘要翻译：半导体衬底包括至少半导体层，第一抗反射层和第二抗反射层的衬底。半导体层设置在基板上。第一防反射层设置在半导体层上。第二防反射层设置在第一防反射层上。第二抗反射层是具有光子转换能力的不连续层。

5. 发明申请

US20100090751A1 Electrical Fuse Structure and Method 审中-公开
标题翻译：电气保险丝结构与方法
公开(公告)号：US20100090751A1
公开(公告)日：2010-04-15
申请号：US12637510
申请日：2009-12-14
申请人： Hsin-Li Cheng , Chia-Jung Lee , Chin-Shan Hou , Wei-Ming Chen
发明人： Hsin-Li Cheng , Chia-Jung Lee , Chin-Shan Hou , Wei-Ming Chen
IPC分类号： H01H85/00 , H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.
摘要翻译：介绍了电熔丝及其编程过程。电熔丝包括在非掺杂或轻掺杂多晶硅层上的下层硅化物层，上层导电层和耦合在下层硅化物层和上层导电层之间的钨接触。钨触点和硅化物层的颈部是电熔丝的可编程部分。通过第一编程阶段实现高后编程电阻，其消耗硅化物层中的硅化物，随后是第二编程阶段，其消耗钨接触中的钨。

6. 发明授权

US07642176B2 Electrical fuse structure and method 失效
标题翻译：电熔丝结构及方法
公开(公告)号：US07642176B2
公开(公告)日：2010-01-05
申请号：US12106759
申请日：2008-04-21
申请人： Hsin-Li Cheng , Chia-Jung Lee , Chin-Shan Hou , Wei-Ming Chen
发明人： Hsin-Li Cheng , Chia-Jung Lee , Chin-Shan Hou , Wei-Ming Chen
IPC分类号： H01L21/326 , H01L21/479
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.
摘要翻译：介绍了电熔丝及其编程过程。电熔丝包括在非掺杂或轻掺杂多晶硅层上的下层硅化物层，上层导电层和耦合在下层硅化物层和上层导电层之间的钨接触。钨触点和硅化物层的颈部是电熔丝的可编程部分。通过第一编程阶段实现高后编程电阻，其消耗硅化物层中的硅化物，随后是第二编程阶段，其消耗钨接触中的钨。

7. 发明申请

US20080189443A1 Wireless communication device 审中-公开
标题翻译：无线通信设备
公开(公告)号：US20080189443A1
公开(公告)日：2008-08-07
申请号：US11700773
申请日：2007-02-01
申请人： Wei-Ming Chen , Yi-Cheng Yu , Chih-Tao Huang
发明人： Wei-Ming Chen , Yi-Cheng Yu , Chih-Tao Huang
IPC分类号： G06F3/00
CPC分类号： G06F1/1698 , G06F1/1616 , G06F1/1656
摘要： A wireless communication device includes an RF module, an audio-processing module, a receiving/transmitting module and a housing. The RF module connected wireless with a notebook computer is used for receiving/transmitting an RF data signal and converting the RF data signal into a respective digital audio signal. The audio-processing module is used to perform bi-directional conversion between digital audio signals and analog audio signals. The receiving/transmitting module is used to input or output the analog audio signals. The housing is used to integrate structurally the RF module, the audio-processing module and the receiving/transmitting module so as to appear the wireless communication device a size as a typical computer memory cartridge that can be accommodated inside a memory extension slot of the notebook computer.
摘要翻译：无线通信设备包括RF模块，音频处理模块，接收/发送模块和外壳。用笔记本电脑无线连接的RF模块用于接收/发送RF数据信号，并将RF数据信号转换成相应的数字音频信号。音频处理模块用于在数字音频信号和模拟音频信号之间执行双向转换。接收/发送模块用于输入或输出模拟音频信号。外壳用于结构化地结合RF模块，音频处理模块和接收/发送模块的集成，以将无线通信设备的尺寸显示为可以容纳在笔记本的存储器扩展槽内的典型的计算机存储盒电脑。

8. 发明授权

US07349234B2 Magnetic memory array 有权
标题翻译：磁存储阵列
公开(公告)号：US07349234B2
公开(公告)日：2008-03-25
申请号：US11119052
申请日：2005-04-29
申请人： Yuan-Ching Peng , Shyue-Shyh Lin , Wei-Ming Chen
发明人： Yuan-Ching Peng , Shyue-Shyh Lin , Wei-Ming Chen
IPC分类号： G11C5/08
CPC分类号： G11C11/15 , G11C5/063
摘要： A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.
摘要翻译：本文公开的磁性随机存取存储器（MRAM）装置包括具有磁阻（MR）堆叠的磁存储器单元阵列。 MRAM阵列还包括耦合到MR堆叠的一系列位线和字线。阵列布局通过增加沿着公共导体的相邻MR堆叠之间的距离而不增加MRAM阵列的总体布局面积来提供相邻存储器单元之间减少的串扰。公开了几个实施例，其中相邻MR堆叠被偏移，使得MR堆叠交错。例如，耦合到公共字线或公共位线的MR堆叠组可以交错。交错布局提供了对于给定MRAM阵列区域的相邻MR堆叠之间的距离增加，从而导致例如在写入操作期间串扰的减少。

9. 发明申请

US20080043543A1 Method for manufacturing, writing method and reading non-volatile memory 审中-公开
标题翻译：制造方法，写入方法和读取非易失性存储器
公开(公告)号：US20080043543A1
公开(公告)日：2008-02-21
申请号：US11889804
申请日：2007-08-16
申请人： Wei-Chung Chen , Ta-Neng Ho , Ti-Wen Chen , Wei-Ming Chen
发明人： Wei-Chung Chen , Ta-Neng Ho , Ti-Wen Chen , Wei-Ming Chen
IPC分类号： G11C7/00 , H01L21/266
CPC分类号： G11C7/02 , G11C7/1012 , G11C7/1051 , G11C7/1078 , G11C7/1087
摘要： A method of manufacturing, programming and reading a non-volatile memory is provided. First, a to-be-coded memory having a plurality of to-be-coded cells arranged in a array is provided. Next, an implanting resist layer is formed on the to-be-coded memory. Then, a mask is disposed on the to-be-coded memory, wherein the number of the partial to-be-coded cells under the openings of the mask is less than the number of remaining to-be-coded cells. Afterwards, a patterned implanting resist layer is formed according to the mask. Next, the exposed to-be-coded cells are ion-implanted to define a plurality of first cells and second cells, wherein each first cell and each second cell record a second bit state and a first bit state respectively. Then, the to-be-coded memory is inversely defined, such that the first cells and the second cells record the first bit state and the second bit state respectively.
摘要翻译：提供了制造，编程和读取非易失性存储器的方法。首先，提供具有排列成阵列的多个被编码单元的被编码存储器。接下来，在被编码存储器上形成植入抗蚀剂层。然后，将掩模设置在待编码存储器上，其中掩模开口下部分待编码单元的数量小于剩余待编码单元的数量。然后，根据掩模形成图案化的植入抗蚀剂层。接下来，暴露的待编码单元被离子注入以限定多个第一单元和第二单元，其中每个第一单元和每个第二单元分别记录第二位状态和第一位状态。然后，被编码的存储器被反向定义，使得第一单元和第二单元分别记录第一位状态和第二位状态。

10. 发明授权

US06794203B2 Method of calculating the real added defect counts 有权
标题翻译：计算真实附加缺陷计数的方法
公开(公告)号：US06794203B2
公开(公告)日：2004-09-21
申请号：US10218591
申请日：2002-08-15
申请人： Wei-Ming Chen , Kun-Yu Liu , Chun-Chieh Chen , Lien-Che Ho
发明人： Wei-Ming Chen , Kun-Yu Liu , Chun-Chieh Chen , Lien-Che Ho
IPC分类号： H01L2166
CPC分类号： H01L21/67288
摘要： The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map process by maximizing the summation of a mapping rate and a catching rate. Second, a wafer is scanned with the proper pre-process sensitivity and a pre-process particle number P1 is recorded. Third, a manufacturing step is processed on the wafer. Fourth, the wafer is scanned with the most sensitive scale of the post-process sensitivities and a post-process particle number P2 is recorded. Finally, the post-process particle number P2 is subtracted from the pre-process particle number P1.
摘要翻译：本发明提供一种制造用于监测室或晶片的性质的附加缺陷计数的方法。首先，通过最大化映射率和捕获率的总和，通过映射到映射过程来确定适当的预处理灵敏度。其次，以适当的预处理灵敏度扫描晶片，并记录预处理颗粒数P1。第三，在晶片上处理制造步骤。第四，用最敏感的后处理灵敏度来扫描晶片，并记录后处理粒子数P2。最后，从预处理粒子数P1中减去后处理粒子数P2。

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