专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07981742B2 Semiconductor device, data element thereof and method of fabricating the same 有权
标题翻译：半导体器件及其数据元件及其制造方法
公开(公告)号：US07981742B2
公开(公告)日：2011-07-19
申请号：US12166430
申请日：2008-07-02
申请人： Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L21/8248
CPC分类号： H01L27/11206 , H01L27/101 , H01L27/112
摘要： A method of fabricating a semiconductor device is provided. The method comprises: (a) providing a first and a second conductor; (b) providing a conductive layer; (c) forming a part of the conductive layer into a data storage layer by a plasma oxidation process, wherein the data storage layer is positioned between the first and the second conductor.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：（a）提供第一和第二导体; （b）提供导电层; （c）通过等离子体氧化工艺将导电层的一部分形成数据存储层，其中数据存储层位于第一和第二导体之间。

2. 发明授权

US07960224B2 Operation method for multi-level switching of metal-oxide based RRAM 有权
标题翻译：基于金属氧化物的RRAM的多层次切换操作方法
公开(公告)号：US07960224B2
公开(公告)日：2011-06-14
申请号：US12388655
申请日：2009-02-19
申请人： Wei-Chih Chien , Kuo-Pin Chang , Yi-Chou Chen , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Wei-Chih Chien , Kuo-Pin Chang , Yi-Chou Chen , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L21/8238
CPC分类号： G11C11/14 , G11C11/54 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2213/32 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： A method for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change among resistance states. The sequence of bias arrangements includes a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state.
摘要翻译：一种用于操作存储器件的方法包括在所选择的金属氧化物存储器元件之间施加一系列偏置布置以在电阻状态之间改变。偏置装置的顺序包括将所选择的金属氧化物存储元件的电阻状态从第一电阻状态改变为第三电阻状态的第一组一个或多个脉冲，以及第二组一个或多个脉冲以改变所选择的金属氧化物存储元件从第三电阻状态到第二电阻状态的电阻状态。

3. 发明授权

US08067815B2 Aluminum copper oxide based memory devices and methods for manufacture 有权
标题翻译：基于氧化铝铜的记忆体及其制造方法
公开(公告)号：US08067815B2
公开(公告)日：2011-11-29
申请号：US12332837
申请日：2008-12-11
申请人： Wei-Chih Chien , Kuo-Pin Chang , Yi-Chou Chen , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Wei-Chih Chien , Kuo-Pin Chang , Yi-Chou Chen , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L29/72
CPC分类号： G11C17/16 , H01L27/101 , H01L27/1021
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括第一电极和第二电极。存储器件还包括二极管和包含氧化铝和氧化铜的抗熔丝金属氧化物存储元件。二极管和金属氧化物存储元件电连接在第一电极和第二电极之间。

4. 发明申请

US20090154222A1 OPERATION METHOD FOR MULTI-LEVEL SWITCHING OF METAL-OXIDE BASED RRAM 有权
标题翻译：基于金属氧化物的RRAM的多级开关操作方法
公开(公告)号：US20090154222A1
公开(公告)日：2009-06-18
申请号：US12388655
申请日：2009-02-19
申请人： Wei-Chih Chien , Kuo-Pin Chang , Yi-Chou Chen , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Wei-Chih Chien , Kuo-Pin Chang , Yi-Chou Chen , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/14 , G11C11/54 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2213/32 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： Memory devices and methods for operating such devices are described herein. A method as described herein for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change the resistance state from a first resistance state in a plurality of resistance states to a second resistance state in the plurality of resistance states. The sequence of bias arrangements comprise a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state.
摘要翻译：这里描述了用于操作这样的设备的存储器件和方法。本文描述的用于操作存储器件的方法包括：在所选择的金属氧化物存储元件上施加偏置布置序列，以将电阻状态从多个电阻状态中的第一电阻状态改变为多个电阻状态中的第二电阻状态阻力状态。偏置装置的顺序包括一个或多个脉冲的第一组，以将所选择的金属氧化物存储元件的电阻状态从第一电阻状态改变到第三电阻状态;以及第二组一个或多个脉冲，以改变所选择的金属氧化物存储元件从第三电阻状态到第二电阻状态的电阻状态。

5. 发明申请

US20100276658A1 Resistive Memory Structure with Buffer Layer 有权
标题翻译：具有缓冲层的电阻式存储器结构
公开(公告)号：US20100276658A1
公开(公告)日：2010-11-04
申请号：US12836304
申请日：2010-07-14
申请人： Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1633 , Y10S438/90
摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.
摘要翻译：存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。记忆元件包括一种或多种金属氧化合物。缓冲层包括氧化物和氮化物中的至少一种。另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。记忆体包括一种或多种金属氧化合物。制造存储器件的方法的一个例子包括形成第一和第二电极。形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

6. 发明申请

US20110189819A1 Resistive Memory Structure with Buffer Layer 审中-公开
标题翻译：具有缓冲层的电阻式存储器结构
公开(公告)号：US20110189819A1
公开(公告)日：2011-08-04
申请号：US13083450
申请日：2011-04-08
申请人： Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/8239
CPC分类号： H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1633 , Y10S438/90
摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.
摘要翻译：存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。记忆元件包括一种或多种金属氧化合物。缓冲层包括氧化物和氮化物中的至少一种。另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。记忆体包括一种或多种金属氧化合物。制造存储器件的方法的一个例子包括形成第一和第二电极。形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

7. 发明授权

US07943920B2 Resistive memory structure with buffer layer 有权
标题翻译：具有缓冲层的电阻式存储器结构
公开(公告)号：US07943920B2
公开(公告)日：2011-05-17
申请号：US12836304
申请日：2010-07-14
申请人： Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/04
CPC分类号： H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1633 , Y10S438/90
摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.
摘要翻译：存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。记忆元件包括一种或多种金属氧化合物。缓冲层包括氧化物和氮化物中的至少一种。另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。记忆体包括一种或多种金属氧化合物。制造存储器件的方法的一个例子包括形成第一和第二电极。形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

8. 发明授权

US07777215B2 Resistive memory structure with buffer layer 有权
标题翻译：具有缓冲层的电阻式存储器结构
公开(公告)号：US07777215B2
公开(公告)日：2010-08-17
申请号：US12176183
申请日：2008-07-18
申请人： Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L47/00
CPC分类号： H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1633 , Y10S438/90
摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.
摘要翻译：存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。记忆元件包括一种或多种金属氧化合物。缓冲层包括氧化物和氮化物中的至少一种。另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。记忆体包括一种或多种金属氧化合物。制造存储器件的方法的一个例子包括形成第一和第二电极。形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

9. 发明申请

US20100277967A1 GRADED METAL OXIDE RESISTANCE BASED SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：基于金属氧化物电阻的半导体存储器件
公开(公告)号：US20100277967A1
公开(公告)日：2010-11-04
申请号：US12431983
申请日：2009-04-29
申请人： MING-DAOU LEE , Erh-Kun Lai , Kuang-Yeu Hsieh , Wei-Chih Chien , Chien-Hung Yeh
发明人： MING-DAOU LEE , Erh-Kun Lai , Kuang-Yeu Hsieh , Wei-Chih Chien , Chien-Hung Yeh
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： H01L45/1608 , G11C13/0007 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/112
摘要： Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.
摘要翻译：描述存储器件以及用于制造的方法和操作方法。如本文所述的存储器件包括位于字线和位线之间的多个存储器单元。多个存储单元中的存储单元包括可编程为包括第一和第二电阻状态的多个电阻状态的二极管和金属氧化物存储元件，存储元件的二极管沿着电流串联布置在对应的字线和相应的位线。该装置还包括偏置电路，以跨越二极管的串联装置和多个存储单元中所选存储单元的存储元件施加偏置装置。

10. 发明授权

US08488362B2 Graded metal oxide resistance based semiconductor memory device 有权
标题翻译：基于分级金属氧化物电阻的半导体存储器件
公开(公告)号：US08488362B2
公开(公告)日：2013-07-16
申请号：US12431983
申请日：2009-04-29
申请人： Ming-Daou Lee , Erh-Kun Lai , Kuang-Yeu Hsieh , Wei-Chih Chien , Chien-Hung Yeh
发明人： Ming-Daou Lee , Erh-Kun Lai , Kuang-Yeu Hsieh , Wei-Chih Chien , Chien-Hung Yeh
IPC分类号： G11C11/00
CPC分类号： H01L45/1608 , G11C13/0007 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/112
摘要： Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.
摘要翻译：描述存储器件以及用于制造的方法和操作方法。如本文所述的存储器件包括位于字线和位线之间的多个存储器单元。多个存储单元中的存储单元包括可编程为包括第一和第二电阻状态的多个电阻状态的二极管和金属氧化物存储元件，存储元件的二极管沿着电流串联布置在对应的字线和相应的位线。该装置还包括偏置电路，以跨越二极管的串联装置和多个存储单元中所选存储单元的存储元件施加偏置装置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式