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    • 8. 发明授权
    • Touch panel having sensing spacers
    • 具有感应间隔件的触摸面板
    • US07843517B2
    • 2010-11-30
    • US12324899
    • 2008-11-28
    • Ming-Che HsiehShih-Yu WangChih-Wei Chu
    • Ming-Che HsiehShih-Yu WangChih-Wei Chu
    • G02F1/1335G02F1/00G02B5/20
    • G02F1/13338G02F1/13439G02F2001/13396G02F2202/02
    • A touch panel including a first substrate, a second substrate, a sealant, a liquid crystal layer, a main spacer, a first sensing spacer, a second sensing spacer, a first opposite electrode and a second opposite electrode is provided. The first substrate has a central area and a peripheral area. The second substrate is disposed opposite to the first substrate. The first sensing spacer is disposed on the central area and between the first and the second substrates. The second sensing spacer is disposed on the peripheral area and between the first and the second substrates. There's a first sensing gap between the first sensing spacer and the first opposite electrode disposed corresponding to the first sensing spacer. There's a second sensing gap between the second sensing spacer and the second opposite electrode disposed corresponding to the second sensing spacer. The first sensing gap is larger than the second sensing gap.
    • 提供了包括第一基板,第二基板,密封剂,液晶层,主间隔件,第一感测间隔件,第二感测间隔件,第一相对电极和第二相对电极的触摸面板。 第一基板具有中心区域和周边区域。 第二基板与第一基板相对设置。 第一感测间隔件设置在中心区域上并且位于第一和第二基板之间。 第二检测间隔件设置在周边区域上并且在第一和第二基板之间。 在第一感测间隔物和与第一感测间隔物相对设置的第一相对电极之间存在第一感测间隙。 第二检测间隔件和对应于第二检测间隔件设置的第二相对电极之间存在第二检测间隙。 第一感测间隙大于第二感测间隙。
    • 9. 发明申请
    • STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION
    • 静电放电保护结构
    • US20100109076A1
    • 2010-05-06
    • US12264879
    • 2008-11-04
    • Shih-Yu WangChia-Ling LuYan-Yu ChenYu-Lien LiuTao-Cheng Lu
    • Shih-Yu WangChia-Ling LuYan-Yu ChenYu-Lien LiuTao-Cheng Lu
    • H01L29/78H01L21/336
    • H01L27/0262H01L27/0251H01L29/7436
    • A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A first doped region of the first conductivity type and a second doped region of the second conductivity type are located in the second well region. A first transistor includes the first doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.
    • 半导体器件包括第一导电类型的第一阱区域,第二导电类型的第二阱区域,第一阱区域内的第二导电类型的源极区域和至少部分地在第二阱区域内的第二导电类型的漏极区域 第二个井区。 与第一阱区的良好接触耦合到源。 第一导电类型的第一掺杂区域和第二导电类型的第二掺杂区域位于第二阱区域中。 第一晶体管包括第一掺杂区域,第二阱区域和第一阱区域。 第一晶体管耦合到开关器件。 第二晶体管包括第二阱区,第一阱区和源极区。 第一和第二晶体管被配置为在ESD事件期间提供电流路径。