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1. 发明授权

US08558300B2 Method for fabricating a flash memory cell utilizing a high-K metal gate process and related structure 有权
标题翻译：利用高K金属栅极工艺和相关结构制造闪存单元的方法
公开(公告)号：US08558300B2
公开(公告)日：2013-10-15
申请号：US12590370
申请日：2009-11-06
申请人： Wei Xia , Xiangdong Chen , Frank Hui
发明人： Wei Xia , Xiangdong Chen , Frank Hui
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11526 , H01L27/11546
摘要： According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.
摘要翻译：根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分电介质层。浮栅包括金属一层的一部分，电介质一层包括第一高k电介质材料。控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

2. 发明申请

US20120039106A1 Programmable Memory Cell with Shiftable Threshold Voltage Transistor 有权
标题翻译：具有可移位阈值电压晶体管的可编程存储单元
公开(公告)号：US20120039106A1
公开(公告)日：2012-02-16
申请号：US13283418
申请日：2011-10-27
申请人： Frank Hui , Xiangdong Chen , Wei Xia
发明人： Frank Hui , Xiangdong Chen , Wei Xia
IPC分类号： G11C17/08
CPC分类号： G11C17/16 , G11C17/18 , H01L27/115
摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.
摘要翻译：根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。可移位阈值电压晶体管具有漏极和栅极短路在一起。编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

3. 发明授权

US08050076B2 One-time programmable memory cell with shiftable threshold voltage transistor 失效
标题翻译：具有可移位阈值电压晶体管的一次性可编程存储单元
公开(公告)号：US08050076B2
公开(公告)日：2011-11-01
申请号：US12462732
申请日：2009-08-07
申请人： Frank Hui , Xiangdong Chen , Wei Xia
发明人： Frank Hui , Xiangdong Chen , Wei Xia
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L27/115
摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.
摘要翻译：根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。可移位阈值电压晶体管具有漏极和栅极短路在一起。编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

4. 发明申请

US20110032742A1 One-time programmable memory cell with shiftable threshold voltage transistor 失效
公开(公告)号：US20110032742A1
公开(公告)日：2011-02-10
申请号：US12462732
申请日：2009-08-07
申请人： Frank Hui , Xiangdong Chen , Wei Xia
发明人： Frank Hui , Xiangdong Chen , Wei Xia
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： G11C17/16 , G11C17/18 , H01L27/115
摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

5. 发明授权

US08363445B2 One-time programmable memory cell 有权
标题翻译：一次性可编程存储单元
公开(公告)号：US08363445B2
公开(公告)日：2013-01-29
申请号：US13283267
申请日：2011-10-27
申请人： Frank Hui , Xiangdong Chen , Wei Xia
发明人： Frank Hui , Xiangdong Chen , Wei Xia
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L27/115
摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.
摘要翻译：根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。可移位阈值电压晶体管具有漏极和栅极短路在一起。编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

6. 发明申请

US20110108903A1 Method for fabricating a flash memory cell utilizing a high-K metal gate process and related structure 有权
标题翻译：利用高K金属栅极工艺和相关结构制造闪存单元的方法
公开(公告)号：US20110108903A1
公开(公告)日：2011-05-12
申请号：US12590370
申请日：2009-11-06
申请人： Wei Xia , Xiangdong Chen , Frank Hui
发明人： Wei Xia , Xiangdong Chen , Frank Hui
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/11526 , H01L27/11546
摘要： According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.
摘要翻译：根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分电介质层。浮栅包括金属一层的一部分，电介质一层包括第一高k电介质材料。控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

7. 发明授权

US08422265B2 Programmable memory cell with shiftable threshold voltage transistor 有权
标题翻译：具有可移位阈值电压晶体管的可编程存储单元
公开(公告)号：US08422265B2
公开(公告)日：2013-04-16
申请号：US13283418
申请日：2011-10-27
申请人： Frank Hui , Xiangdong Chen , Wei Xia
发明人： Frank Hui , Xiangdong Chen , Wei Xia
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L27/115
摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.
摘要翻译：根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。可移位阈值电压晶体管具有漏极和栅极短路在一起。编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

8. 发明申请

US20120039108A1 One-Time Programmable Memory Cell 有权
标题翻译：一次性可编程存储单元
公开(公告)号：US20120039108A1
公开(公告)日：2012-02-16
申请号：US13283267
申请日：2011-10-27
申请人： Frank Hui , Xiangdong Chen , Wei Xia
发明人： Frank Hui , Xiangdong Chen , Wei Xia
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L27/115
摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.
摘要翻译：根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。可移位阈值电压晶体管具有漏极和栅极短路在一起。编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

9. 发明授权

US09129856B2 Method for efficiently fabricating memory cells with logic FETs and related structure 有权
标题翻译：用逻辑FET和相关结构有效地制造存储单元的方法
公开(公告)号：US09129856B2
公开(公告)日：2015-09-08
申请号：US13179248
申请日：2011-07-08
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： H01L27/115 , H01L21/8238
CPC分类号： H01L27/11534 , H01L21/823842
摘要： According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common substrate in the memory and logic regions. The method also includes forming a polysilicon segment over the lower dielectric segment in the memory region, while concurrently forming a sacrificial polysilicon segment over the lower dielectric segment in the logic region. Furthermore, the method includes removing from the logic region the lower dielectric segment and the sacrificial polysilicon segment. The method additionally includes forming a high-k segment in the logic region over the common substrate, and in the memory region over the polysilicon segment and forming a metal segment over the high-k segment in the logic and memory regions. An exemplary structure achieved by the described exemplary method is also disclosed.
摘要翻译：根据一个示例性实施例，用于同时制造具有公共衬底中的逻辑区域的存储区域的方法包括在存储器和逻辑区域中的公共衬底中形成下部介电段。该方法还包括在存储器区域中的下介电段上形成多晶硅段，同时在逻辑区域中的下介电段上同时形成牺牲多晶硅段。此外，该方法包括从逻辑区域去除下介电段和牺牲多晶硅段。该方法还包括在公共衬底上的逻辑区域中形成高k区段，并在多晶硅区段上的存储区域中形成高k区段，并在逻辑和存储区域中的高k区段上形成金属区段。还公开了通过描述的示例性方法实现的示例性结构。

10. 发明授权

US08748277B2 Method for fabricating a MOS transistor with reduced channel length variation 有权
标题翻译：具有减小的沟道长度变化的MOS晶体管的制造方法
公开(公告)号：US08748277B2
公开(公告)日：2014-06-10
申请号：US13613520
申请日：2012-09-13
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

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